Divider Discussion D 7 3 Example 20 Division

Divider Discussion D 7. 3 Example 20

Division 1010 1101 10000111 1101 00111 0000 01111 1101 0000 0101 10 13 135 13 05

Division 8 -bit/4 -bit = 4: 4 1010 1101 10000111 1101 00111 0000 01111 1101 0000 0101

Division 8 -bit/4 -bit = 4: 4 1. Store the numerator in the concatenation of n 1: n 2 2. Store the denominator in d 3. Repeat 4 times: Shift n 1: n 2 left one bit If n 1 > d n 1 = n 1 – d; n 2[0] = 1; 4. quot = n 2; rem = n 1[3: 0];

div 4 a. vhd Combinational divide -- Example 20 a: 4 -bit divider library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. STD_LOGIC_unsigned. all; entity div 4 a is port( numer : in STD_LOGIC_VECTOR(7 downto 0); denom : in STD_LOGIC_VECTOR(3 downto 0); quotient : out STD_LOGIC_VECTOR(3 downto 0); remainder : out STD_LOGIC_VECTOR(3 downto 0) ); end div 4 a;

architecture div 4 a of div 4 a is begin process(numer, denom) variable d, n 1: STD_LOGIC_VECTOR(4 downto 0); variable n 2: STD_LOGIC_VECTOR(3 downto 0); begin d : = '0' & denom; n 2 : = numer(3 downto 0); n 1 : = '0' & numer(7 downto 4); for i in 0 to 3 loop n 1 : = n 1(3 downto 0) & n 2(3); n 2 : = n 2(2 downto 0) & '0'; if n 1 >= d then n 1 : = n 1 - d; n 2(0) : = '1'; end if; end loop; quotient <= n 2; remainder <= n 1(3 downto 0); end process; end div 4 a;

Divide Simulation

div synthesized circuit denom(3: 0) remain(3: 0) quot(3: 0) numer(7: 3) numer(2: 0)

Top-level Design