Distributed Algorithms 22903 Shared objects linearizability waitfreedom and
Distributed Algorithms (22903) Shared objects: linearizability, wait-freedom and simulations Lecturer: Danny Hendler Most of this presentation is based on the book “Distributed Computing” by Hagit attiya & Jennifer Welch. Some slides are based on presentations by Maurice Herlihgy & Nir Shavit.
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Shared Objects (cont’d) • Each object has a state – Usually given by a set of shared memory fields • Objects may be implemented from simpler base objects • Each object supports a set of operations – Only way to manipulate state – E. g. – a shared counter supports the fetch&increment operation 3
Shared Objects Correctness of a sequential counter • fetch&increment, applied to a counter with value v, returns v and increments the counter’s value to (v+1). • Values returned by consecutive operations: 0, 1, 2, … But how do we define the correctness of a shared counter? 4
Shared Objects Correctness (cont’d) fetch&inc q. enq(x) Invocation Response q. deq(y) fetch&inc q. enq(y) fetch&inc q. deq(x) fetch&inc time There is only a partial order between operations! 5
Shared Objects Correctness (cont’d) An invocation calls an operation on an object. c. f&I () method object arguments 6
Shared Objects Correctness (cont’d) An object returns the response of the operation. c: 12 response object 7
Shared Objects Correctness (cont’d) A sequential object history is a sequence of matching invocations and responses on the object. Example: a sequential history of a FIFO queue q. enq(3) q: void q. enq(7) q: void q. deq() q: 3 q. deq() q: 7 8
Shared Objects Correctness (cont’d) Sequential specification The correct behavior of the object in the absence of concurrency: a set of legal sequential object histories. Example: the sequential spec of a counter H 0 : H 1 : H 2 : H 3 : H 4 : . . . c. f&i() c: 0 c. f&i() c: 1 c. f&i() c: 2 c. f&i() c: 3 9
Shared Objects Correctness (cont’d) Linearizability An execution is linearizable if there exists a permutation of the operations on each object o, , such that: • is a sequential history of o • preserves the partial order of the execution. 10
Example lin ea q. enq(x) q. enq(y) q. deq(y) riz ab le q. deq(x) time (6) 11
Example no t q. enq(x) q. deq(y) lin ea riz ab le q. enq(y) time (5) 12
Example lin ea q. enq(x) riz ab le q. deq(x) time (4) 13
Example mu lti plile q. enq(x) q. deq(y) q. enq(y) neo arrd iezra sb l. Oe. K q. deq(x) time (8) 14
Wait freedom Wait-freedom An algorithm is wait-free if every operation terminates after performing some finite number of events. Wait-freedom implies that there is no use of locks (no mutual exclusion). Thus the problems inherent to locks are avoided: • Deadlock • Priority inversion 15
Wait-free linearizable implementations Example: the sequential spec of a register H 0: H 1: H 2: H 3: H 4: . . . r. read() r: init r. write(v 1) r: ack r. read() r: v 1 r. write(v 1) r: ack r. write(v 2) r: ack r. read() r: v 2 Read returns the value written by last Write (or init value if there were no preceding writes) 16
Wait-free (linearizable) register simulations multi-reader/multi-writer register multi-reader/single-writer register (Multi-valued) single-reader/single-writer register Binary single-reader/single-writer register 17
A wait-free (linearizable) implementation of a single-writer-single-reader (SRSW) multivalued register from binary SRSW registers Initially B[0]…B[k-1]=0, B[i]=1 (i is the initial value of R) Read(R) Return the index of the highest entry of B that equals 1 Write(R, v) Write 1 to B[v], clear the entry corresponding to the previous value (if other than v). Would the above implementation of a k-valued register (initialized to i) work? No! 18
An example of a non-linearizable execution = linearization point Initially B[0]…B[2]=0, B[3]=1 Return 2 Read B[0] Return Read B[2] 0 Return Read 0 B[1] Write(1) Write 1 to B[1] Ack Write 0 Ack to B[3] Return 1 Write(2) Write 1 to B[2] Write(1) precedes Write(2) AND Read(2) precedes Read(1). This is not linearizable! Read Return 1 Read Return B[0] 0 B[1] 1 Ack Write 0 to B[1] Ack 19
A Wait-free Linearizable Implementation Initially B[v]=1 and all other entries equal 0, where v is the initial value of R. Read(R) 1. i: =0 2. while B[i]=0 do i: =i+1 3. up: = i, v: =i 4. for i=up – 1 downto 0 do 5. if B[i]=1 then v: =i 6. return v Write(R, v) 1. B[v]: =1 2. For i: =v-1 downto 0 do B[i]: =0 3. return ack 20
The linearization order Write 2(R, 4) Write 1(R, 1) Read 1(R, init) Read 2(R, 4) Read 3(R, 4) Writes linearized first All reads from a specific write linearized after it, in their realtime order. Write 3(R, 3) Read 4(R, 3) Write 4(R, 1) Read 5(R, 1) Read 1(R, init) Write 1(R, 1) Write 2(R, 4) Read 3(R, 4) Write 3(R, 3) Read 4(R, 3) Write 4(R, 1) Read 5(R, 1) 21
Correctness proof for the SRSW multi-valued register simulation 22
SRSW multi-valued register correctness proof Wait freedom Trivial from the code (no loops) Linearizability Proof partitioned to the following 4 cases: 1. The order between write operations is maintained (follows from construction) 2. If R precedes W in E, then it precedes it in (triv. ) 3. The order between read operations is maintained 4. If W precedes R in E, then it precedes it in We'll now see the proof for case 4. 23
Illustration for Lemma 1 v 1 u 1 0 Written by W 1 0 B 24
Illustration for Lemma 1 v 1 Written by W 2 v 1 0 u 0 1 0 Written by W B Written by W 1 25
Illustration for Lemma 2 E: π: W’(v’) R W(v) R (v’) W(v) Case 1: v’ ≤ v v 1 Written by W v’ 0 0 01 0 0 Written by W’ 26
Illustration for Lemma 2 (cont’d) E: π: W’(v’) R W(v) R (v’) W(v) Case 2: v’ > v v’ 1 Written by W’’ v 0 1 Written by W W’’(x) From Lemma 1, R returns a value written by an operation that follows W’’. 27
A wait-free Implementation of a (muti-valued) multi-reader register from (multi-valued) SRSW registers. 31
Would this work? SRSW Val[i]: The value written by the writer for reader pi Read(R) by pi 1. return Val[i] Write(R, v) 1. For i: =0 to n-1 do Val[i]: =v 2. return ack Is the algorithm wait-free? Yes Is the algorithm linearziable? Nope 32
An example of a non-linearizable execution = linearization point Initially Val[0]=Val[1]=0 Pw: Write(1) Write 1 Ack Write 1 to Val[0] to Val[1] P 0: Ack Read Val[0] Return 1 Read P 1: Read(1) precedes Read(0). This is not linearizable! Read Val[1] Return 0 33
A proof that: no such simulation is possible, unless some readers…write! 34
A wait-free implementation of a (muti-valued) multireader register from (multi-valued) SRSW registers. Data structures used • Values are pairs of the form: <val, sequence-number>. • Sequence-numbers are ever increasing. Val[i]: The value written by pw for reader pi, for 1 ≤ i ≤ n Report[i, j]: The value returned by the most recent read operation performed by p i; written by pi and read by pj, 1 ≤ i, j ≤ n. 35
A wait-free implementation of a multi-reader register from SRSW registers (cont’d). Initially Report[i, j]=Val[i]=(v 0, 0), where v 0 is R’s initial value. Read(R) ; performed by process pr 1. 2. 3. 4. 5. (v[0], s[0]): =Val[r] ; most recent value written by writer for (i: =1 to n do) (v[i], s[i])=Report[i, r] ; most recent value reported to pr by reader pi Let j be such that s[j]=max{s[0], s[1], …, s[n]} for i: =1 to n do Report[r, i]=(v[j], s[j]) ; pr reports to all readers Return (v[j]) Write(R, v) ; performed by the single writer 1. 2. 3. seq: =seq+1 for i=1 to n do Val[i]=(v, seq) return ack 36
The linearization order Write(v 1, 1) Read 1(init, 0) Read 2(v 1, 1) Writes linearized first Reads considered according to increasing order of response, and put after the write with same sequence ID. Write(v 2, 2) Write(v 3, 3) Write(v 4, 4) Read 5(v 4, 4) Read 4(v 2, 2) Read 3(v 2, 2) Read 1(init, 0) Write(v 1, 1) Read 2(v 1, 1) Write(v 2, 2) Read 3(v 2, 2) Read 4(v 2, 2) Write(v 3, 3) Write(v 4, 4) Read 5(v 4, 4) 37
A wait-free Implementation of a multireader-multi-writer register from multi-reader-single-writer registers 38
A wait-free implementation of a MRMW register from MRSW registers. Data structures used • Values are pairs of the form: <val, sequence-number>. • Sequence-numbers are ever increasing. TS[i]: The vector timestamp of writer pi, for 0 ≤ i ≤ m-1. Written by pi and read by all writers. Val[i]: The latest value written by writer pi, for 0 ≤ i ≤ m-1, together with the vector timestamp associated with that value. Written by pi and read by all n readers. 39
Concurrent timestamps • Provide a total order for write operations • The total order respects the partial order of write operations • Timestamp implemented as vectors • Ordered by lexicographic order • Each writer increments its vector entry 40
Concurrent timestamps example Writer 1 <1, 0, 0> Writer 2 Writer 3 TS[1] 0 <0, 0, 0> TS[2] <0, 0, 0> TS[3] <0, 0, 0> Order: <0, 0, 0> 41
Concurrent timestamps example Writer 1 Writer 2 <1, 0, 0> <1, 1, 0> Writer 3 TS[1] <1, 0, 0> TS[2] <0, 0, 0> TS[3] <0, 0, 0> Order: <0, 0, 0> <1, 0, 0> 42
Concurrent timestamps example Writer 1 Writer 2 <1, 0, 0> <1, 1, 0> <1 , 2, 1> <1 , 1, 1> Writer 3 TS[1] <1, 0, 0> TS[2] <1, 1, 0> TS[3] <0, 0, 0> Order: <0, 0, 0> <1, 1, 1> <1, 2, 1> 43
A wait-free Implementation of a MRMW register from MRSW registers. Initially TS[i]=<0, 0, …, 0> and Val[i] equals the initial value of R Read(R) ; performed by reader pr 1. 2. 3. for i: =0 to m-1 do (v[i], t[i]): =Val[i] ; v and t are local Let j be such that t[j]=max{t[0], …, t[m-1]} ; Lexicographic max Return v[j] Write(R, v) ; performed by the writer pw 1. 2. 3. ts=New. CTS() ; Writer pw obtains a new vector timestamp Val[w]: =(v, ts) return ack Procedure New. CTS() ; called by writer pw 1. for i: =0 to m-1 do 2. lts[i]: =TS[i]. i ; extract the i’th entry from TS of the i’th writer 3. lts[w]=lts[w]+1 ; Increment own entry 4. TS[w]=lts ; write pw’s new timestamp 44 5. return lts
The linearization order Writer 1 Writer 2 Reader 1 Reader 2 Write(v 1, <1, 0>) Write(v 2, <1, 1>) Read 1(init, <0, 0>) Read 2(init, <0, 0>) Writes linearized first by timestamp order Reads considered according to increasing order of response, and put after the write with same timestamped Write(v 4, <2, 2>) Write(v 3, <1, 2>) Read 4(v 2, <1, 1>) Read 5(v 4, <2, 2>) Read 3(v 2, <1, 1>) Read 1(init, <0, 0>) Read 2(init, <0, 0>) Write(v 1, <1, 0>) Write(v 2, <1, 1>) Read 3(v 2, <1, 1>) Read 4(v 2, <1, 1>) Write(v 3, <1, 2>) Write(v 4, <2, 2>) Read 5(v 4, <2, 2>) 45
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