DIGITALLY CONTROLLED OSCILLATORS DCO Alicia Klinefelter ECE 7332

DIGITALLY CONTROLLED OSCILLATORS (DCO) Alicia Klinefelter ECE 7332 Spring 2011

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 2

WHY ARE ADPLLS USEFUL? Problems with analog implementation § Design and verification § Settling time § 20 – 30 ms in CPPLLs § 10 ms in the ADPLL § Implementation cost § Custom blocks § Loop Filter § High Leakage current § Large capacitor (2) area § Charge Pump § Low output resistance § Mismatch between charging current and discharging current § Phase offset and reference spurs 3

ALL-DIGITAL PLL (ADPLL) TOPOLOGY DCO ref(t) Time-to-Digital Converter (TDC) Digital Loop Filter out(t) Divider 4

ADPLL: TIME-TO-DIGITAL CONVERTER DCO ref(t) div(t) Time-to-Digital Converter (TDC) Digital Loop Filter out(t) Divider Delay chain structure sets resolution Mismatch causes linearity issues Resolution: want low quantization noise Architectures 5 [1, Perrott]

ADPLL: DIGITAL LOOP FILTER DCO ref(t) Time-to-Digital Converter (TDC) Digital Loop Filter out(t) Divider Compact area Insensitive to leakage 6

ADPLL: DCO ref(t) Time-to-Digital Converter (TDC) Digital Loop Filter out(t) Divider Replaces the VCO from analog implementations Consumes 50 -70% of overall ADPLL power Generally consists of a digital controller implementing frequency acquisition algorithm and oscillator. 7

METRICS Power Consumption @ Frequency Phase Noise § Measured with respect to a frequency offset from the carrier § The units, d. Bm/Hz, define noise power contained in a 1 Hz bandwidth Jitter LSB Resolution (ps) Tuning range Note: bit resolution is rarely mentioned § Does not seem to have drastic impact on tuning range 8

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 9

EARLY ARCHITECTURES: ANALOG TUNING Straightforward approach § DAC + VCO Varactors used initially Problem with varactors: § Capacitance not very linear with input voltage. § For digital tuning, need flat regions. [3, Xu] 10

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 11

OSCILLATORS: RING OSCILLATOR 12

OSCILLATORS: LC OSCILLATOR 240 um [4, Thiel] 13

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 14

NOVELTY: FULLY DIGITAL TUNING Weighted capacitor networks replaced varactors Concept of fine and coarse tuning introduced § Coarse (binary weighted) lacks monotonicity § Fine (unit weighted) has monotonicity but complex control 15

TECHNIQUE : DITHERING To increase resolution, many systems use ΣΔ modulators for dithering the input to the unit caps. § Unit cap determines gain of DCO Recall, ΣΔ modulators are oversampling converters and produces output pulses proportional to signal changes. § Quantization noise effects § Phase noise goes down as frequency increases [1, Perrott] 16

NOISE ANALYSIS: DITHERING [1, Perrott] x[n] H(s) y(t) 17

NOISE ANALYSIS: DITHERING [1, Perrott] 18

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 19

DELAY CELLS: DCM Many traditional delay lines are simple inverters Chain of tri-state inverters in parallel Driving capability modulation (DCM) Changes the driving current of each delay cell by controlling number of enabled tri-state buffers/inverters Bad power, linearity 20

DELAY CELLS: HYSTERESIS Hysteresis delay cells (HDC) are relatively new in low power (2007 - ). Trade off power and delay resolution. Fewer needed to acquire the delay of a many traditional delay cells. § HDCs have wider operating range Control of driving current to obtain different propagation delay [2] 21

IMPLEMENTATION Application: Wireless body area networks § Relaxes phase noise requirement Oscillator structure based on a power-of-2 delay stage DCO (P 2 -DCO) architecture § Each delay stages is ½ delay of previous 80 um x 80 um in 90 nm CMOS 5. 4 u. W @ 3. 4 MHz, 1 V supply Presents two novel HDC topologies § Improves power-to-delay and area-to-delay ratios 22

IMPLEMENTATION: DELAY CELLS Uses different hysteresis cells for different tuning stages Need for decoder removed due to power of two delay Header and footer rarely turned on at same time Leads to voltage scaling of the cell with hysteresis [9] 23

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 24

ARCHITECTURE: STANDARD CELL As technology migrates, push towards standard cell implementations for portability. Goal: implement DCO in HDL Ring oscillators always used for synthesizeable DCO Limits implementation options § Most delay cells inverters and NANDs § Controllers simply digital logic 25

PAPER HIGHLIGHTS Segmented delay line, hysteresis delay cells, and uses standard cells: ultra portable! 140 u. W (@200 MHz) with 1. 47 -ps resolution Segmented delay line power gating saves ~25 -75% of power § Dependent on operating frequency [2] 26

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 27

CONTROLLER: LOCKING TIME New DCO tuning word (OTW) presetting technique to reduce settling time Three stages in ADPLL § PVT calibration § Frequency Acquisition § Tracking (locked) Each mode is a search algorithm, each has its own scheme For ring oscillator, controller implemented in digital logic For LC oscillator, controller is capacitor bank 28

CONTROLLER: FASTER ALTERNATIVE Paper [4] designed a new, faster locking algorithm for frequency acquisition. Locks in 18 clock cycles Binary search typically used [4] 29

CONTROLLER: FASTER ALTERNATIVE 1. PFD produces gain and fast/slow pulse 2. Mux selects fast/slow gain value 3. Gain value like the charge pump [4] 1. As DCO frequency differs more from target, gain increases 4. Use previous gain with new gain to determine new guess value 30

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 31

NOVELTY: SUBTHRESHOLD 1. 9 GHz DCO in 0. 13 um technology 2 x 2 mm 2 using 6 metal layers Supply voltage at 0. 5 V, 100 u. W power § More device transconductance (g m ) is available for a given bias current Application: frequency synthesizer in wireless transceiver Between calibration, oscillator runs free until next tuning cycle (TX/RX) § Other circuitry turned off No external components used (even with LC oscillator) 32

OSCILLATOR: LC BASED Differential NMOS only for high output swing for low input voltages Inductance [10] § Want high Q determines overall Q of system, startup current, and power consumption § Used bondwire inductances Want 1 f. F LSB from caps, but a problem when wiring parasitics on same order of magnitude 33

CHALLENGE: SMALL CAPACITORS Capacitor matching a problem for small unit capacitors Varactors could work [10] § Need flat areas of curve § Testing required to find input voltages of such areas Switched capacitor implementation using linear capacitors proposed § Routing parasitics reduced 34

OUTLINE Basic Topology of All Digital PLLs (ADPLL) § Where does the DCO fit in? Early Architectures Oscillator Background Current Research § Seminal: All Digital Control [14] § Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process § Hysteresis Delay Cell [9] § A Sub-10 -μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications § Portability [2] § An Ultra-Low-Power and Portable Digitally Controlled Oscillator for So. C Applications § Frequency Acquisition and Locking [4] § A 1. 7 m. W all digital phase-locked loop with new gain generator and low power DCO § Subthreshold Operation [10] § A 100μW, 1. 9 GHz oscillator with fully digital frequency tuning Comparison of Results 35

DESIGN COMPARISONS: POWER Power Op. Freq Voltage 5. 4 u. W 3. 4 MGHz 1 V 5. 2 uw 3. 89 MHz 1 V 8 m. W 12. 3 MHz 1. 2 V 1. 7 m. W 20 MHz 1 V 166 u. W 163. 2 MHz 1 V 140 u. W 200 MHz 1 V 110 u. W 200 mh. Z 0. 8 V 75. 9 u. W 239. 2 MHz 1 V 340 u. W 450 MHz 1. 8 V 1. 7 m. W 560 MHz 1. 2 V 2. 3 m. W 800 MHz 0. 9 V 23. 3 m. W 1 GHz 1. 8 V 5. 5 m. W 5. 6 GHz 0. 7 V 36

DESIGN COMPARISONS: FREQ OFFSET 37

DESIGN COMPARISONS: TUNING RANGE 38

RESOURCES CPPSIM Tutorials § [1, Perrot] PLL Digital Frequency Synthesizers § [2, Perrot] PLL Voltage Controlled Oscillators All papers in the bibliography section of Wiki were used for plot generation Papers [2], [4], [9], [10], [14] addressed in presentation [3, Xu] Xu, L. (2006, May 18). Digitally controlled oscillator. Retrieved from http: //www. ecdl. tkk. fi/education/4198/pdf/dco_lxu. pdf [4, Thiel] Thiel, B. T. ; Neyer, A. ; Heinen, S. ; , "Design of a low noise, low power 3. 05– 3. 45 GHz digitally controlled oscillator in 90 nm CMOS, " Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph. D. , vol. , no. , pp. 228 -231, 12 -17 July 2009. 39

OVERVIEW Move to digital PLL implementations motivated by So. C applications New digital circuits in ADPLL: TDC, filter, DCO Ring oscillators versus LC oscillators Current Research § Initial digital tuning with sigma-delta dithering § Delay cells § Portability § Frequency acquisition algorithm § Sub-threshold operation QUESTIONS? 40