Digital Technology and Computer Fundamentals Chapter 3 Sequential

Digital Technology and Computer Fundamentals Chapter 3 Sequential Logic Circuits P. 3. 1

Objectives n At the end of this chapter, you should be able to: u define what is a sequential circuit; u draw the circuit diagram of an SR flipflop and explain its function; u draw the circuit diagram of a JK flipflop and explain its function; u explain the functions of D-type and Ttype flip-flops; 2

Objectives (Cont’d) u differentiate the functions of triggering control; u identify the representations for different types of triggering in a circuit symbol; u explain the functions of direct inputs; 3

Objectives (Cont’d) u explain the operations of shift register circuits; and u explain the operations of the asynchronous and synchronous counter circuits. 4

References n n n Thomas C. Bartee, "Digital Computer Fundamentals, " sixth edition, Mc. Graw -Hill Publishing Company. Richard S. Sandige, "Modern Digital Design, " Mc. Graw-Hill Publishing Company. Theodore F. Bogart Jr. , "Introduction to Digital Circuits, "” Mc. Graw-Hill Publishing Company. 5

Introduction n Those whose outputs depend on the state of inputs and the previous state of the outputs. Able to remember a logic value. Several types of sequential logic circuits. u flip-flops u counters u shift registers. 6

Flip Flop n n n A bi-stable element. Two stable states, 1 or 0. Able to store a digital value. Depends on the input and the previous value stored. Basic elements of a memory device in a digital computer. The outputs of Q and are complemented to each other. 7

Flip Flop (Cont’d) n n n To understand, one must be familiar with the functions of logic gates. NAND gate: Output is 1 whenever there is a 0 at the inputs. NOR gate: Output is 0 whenever there is a 1 at the inputs. 8

Flip Flop (Cont’d) n n Propagation delay of the logic gates. Outputs of the logic gates take time to response to input changes. Outputs change in response to the change of inputs and The previous change of the outputs. Time required to settle to a stable state, i. e. the final values of outputs. 9

Flip Flop (Cont’d) n n An initial value, 1 or 0, must be assigned to the previous outputs for deducing the final output values. We usually use the symbol Qn to denote the initial (or previous) value of the output and Qn+1 to denote the new value of the stable output. 10

S-R (Set-Reset) Flip Flop n n S-R flip-flop is the simplest one. Can be made by any logic gates. 11

S-R Flip Flop (Cont’d) n n Case 1: S = R = 0. Assume Q = 0 and = 1. u Substitute values into eq. 3. 1 and 3. 2 u New output values: Q = 0 and = 1. n If initially, Q = 1 and u New n =0 outputs are: Q = 1 and -Q = 0. Conclusion: outputs, Q and -Q, are unchanged if both inputs are 0. 12

S-R Flip Flop (Cont’d) n n Case 2: S = 0, R = 1. Assume Q = 0 and -Q = 1. u Substitute values into eq. 3. 1 and 3. 2, u New output values: Q = 0 and -Q = 1. n If Q = 1 and -Q = 0 are initial state u New outputs: Q = 0 and -Q = 0. u Not a stable state. u Subsequent changes are illustrated in timing table. 13

S-R Flip Flop (Cont’d) n n n Time sequence starts from left to right. Adjacent columns represent a time interval, the propagation delay. Output values at time tn determined by values of the gate inputs at time tn-1. 14

S-R Flip Flop (Cont’d) n n n The outputs Q and -Q settle at time t 3. Their values are 0 and 1 respectively. Concluion: The output Q is reset to 0 when the S is 0 and R is 1. 15

S-R Flip Flop (Cont’d) n n Case 3: S = 1; R = 0. If initially, Q = 0 and -Q = 1. u New output values are: Q = 0 and -Q = 0. u Analysis with the timing table required. 16

S-R Flip Flop (Cont’d) u Values of the Q and -Q settle at time t 3 u Values are 1 and 0 respectively. n If Q = 1 and -Q = 0 are the initial state u New outputs are same: Q = 1 and -Q = 0. n Conclusion: The output Q is set to 1 when the S is 1 and R is 0. 17

S-R Flip Flop (Cont’d) n n n Case 4: S = 1; R = 1. The outputs will be all 0 no matter what their initial values are. If then, the inputs are all reset to 0: u race happens between the logic gates. u Which output is 1 cannot be determined. n Conclusion: this case should never happen in a practical circuit. 18

S-R Flip Flop (Cont’d) n n n Truth table of the S-R flip-flops Different circuits can be found from the same truth table. For example: using NAND gates as in lecture notes. 19

J-K Flip Flop n n Disadvantage of the S-R flip-flop: only three cases of inputs are used. The J-K flip-flop is designed to overcome such limitation. 20

J-K Flip Flop (Cont’d) 21

J-K Flip Flop (Cont’d) 22

J-K Flip Flop (Cont’d) n Case 1: J = 0; K = 0. u Outputs of the gates G 1 and G 2, will be 1 regardless the values of Q and n Conclusion: Q and unchanged. will remain 23

J-K Flip Flop (Cont’d) n n Case 2: J = 0; K = 1. Initially, Q is 0 and -Q is 1 u Substituting all the values into the Eq. 3. 3 to Eq. 3. 6 u The final values of G 1, G 2, Q and -Q are 1, 1, 0, and 1 respectively. 24

J-K Flip Flop (Cont’d) n Initially, Q is 1 and -Q is 0 u Analysis with the timing table required. 25

J-K Flip Flop (Cont’d) n Conclusion: Outputs Q and -Q will be 0 and 1 respectively regardless their initial values if the inputs J and K are 0 and 1 respectively. 26

J-K Flip Flop (Cont’d) n n Case 3: J = 1; K = 0. Initially, Q is 0 and -Q is 1 u Substituting all the values into the Eq. 3. 3 to Eq. 3. 6 u Analysis with timing table 27

J-K Flip Flop (Cont’d) u The final values of G 1, G 2, Q and are 1, 1, 1, and 0 respectively. 28

J-K Flip Flop (Cont’d) n Initially, Q is 1 and -Q is 0 u The stable values of G 1, G 2, Q and -Q are 1, 1, 1, and 0 respectively. n Conclusion: Outputs Q and -Q will be 1 and 0 respectively regardless their initial values if the inputs J and K are 1 and 0 respectively. 29

J-K Flip Flop (Cont’d) n Case 4: J = 1; K = 1. u Analysis of this case must make use of the timing table. 30

J-K Flip Flop (Cont’d) u Setting both J and K inputs at 1 indefinitely will make the outputs change indefinitely. n The real effect of such input change is to make the output change from 0 to 1 or from 1 to 0. 31

J-K Flip Flop (Cont’d) n Truth table of J-K flip-flops. 32

Symbols of the S-R and J-K flip-flops n Circuit symbols of basic flip-flops. 33

D-type Flip-Flop n Truth table and circuit symbol 34

T-type Flip-Flop n Truth table and circuit symbol 35

Triggering of flipflop n With a timing diagram, we can forecast the behavior of a flip-flop 36

Triggering of flipflop (Cont’d) n n n A flip-flop is triggered by the changes at its inputs. Such triggering has immediate effect on the output. Output will be out of control if unwanted situation happens Need certain control on this triggering. Use a clock signal. 37

Clock Signal 38

Triggering with Clock n n n Level-triggered (clocked) A flip-flop responses to the input changes when the clock is at logical 1 is called a positive clocked (positive level-triggered) flip-flop. A negative clocked (negative leveltriggered) flip-flop responses to the input changes when the clock is at logical 0. 39

Triggering with Clock (Cont’d) n n n Edge-triggered A flip-flop responses to the input changes when the clock changes from logical 0 to logical 1 is called a positive edge-triggered flip-flop. A negative edge-triggered flip-flop responses to the input changes when the clock changes from logical 1 to logical 0. 40

Positive clocked SR Flip-Flop n Truth table and circuit symbol 41

An Example n Waveform of a positive clocked SR FF 42

Negative clocked Dtype Flip-Flop n Truth table and circuit symbol 43

Positive edgetriggered T-type Flip -Flop n Truth table and circuit symbol 44

Negative edgetriggered J-K Flip. Flop n Truth table and circuit symbol 45

Another Example n Waveform of a negative clocked JKFF 46

More Example n Waveform of a negative edgetriggered JK FF 47

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Direct inputs n n n Direct inputs allow the users to assign the state of a flip-flop directly without going through the normal inputs. An example: a negative edge-triggered J-K flip-flop with direct preset and clear inputs. Q will be set to logical 1 if PS, preset, is 0. If Clr, clear, is 0, Q output will be reset to 0, i. e. Low activated. 49