Digital Systems Design 2 VHDL Modeling Behaviour Ref

Digital Systems Design 2 VHDL: Modeling Behaviour Ref. “VHDL Starter’s Guide”, Sudhakar Yalamanchili, Prentice Hall, 1998 Veton Këpuska

Modeling Behavior with VHDL u u Presented VHDL constructs (e. g. , CSAs) are limited in modeling only certain class of digital components. In order to be able to describe and model a larger set of digital components a more powerful language construct is needed. The process construct of VHDL provides the basis for these descriptions. n 9/15/2020 It is a construct that can model: u the behavior of components that are much more complex than delay elements through CSA constructs, and u systems at higher level of abstraction. Veton Këpuska 2

VHDL- Process Construct u u Up to this point, presented VHDL language and modeling concepts were derived from the operational characteristics of digital circuits (where the design is represented as a schematic of concurrently operating components). Each component is characterized by the generation of events on output signals in response to events on input signals. These output events may occur after a component dependent propagation delay. This relationship is captured by CSA statement that explicitly relates n n n u u input signals, output signals, and propagation delays. CSAs are convenient constructs for cases when components correspond to gates or switch level models of transistors. For constructing models of complex components such as CPUs, memory modules, or communication protocols, such a model of behavior can be quite limiting. 9/15/2020 Veton Këpuska 3

VHDL- Process Construct u u For modeling components such as memories, the state information is necessary to be retained and being able just to compute output signals as function of values of the input signals is not sufficient. Memory Model: R W DO DI Memory ADDR 9/15/2020 Veton Këpuska 4

VHDL Process example: Memory Model u Memory can be implemented using conventional sequential programming constructs: n n n 9/15/2020 Memory can be implemented as an array. Address value can be used to index this array. Depending on the value of the control signals one can determine read from array or write into array operation. This behavior can be realized in VHDL by using sequential statements in the process construct. Veton Këpuska 5

VHDL Process example: Memory Model u Generic process declaration and syntax. process_name: process (signal 1, signal 2, …, signal. N) -- declarative region variable-names: variable-type; type-name is (value-list); constant-name: type-name : = value; begin -- process body region where conventional programming constructs can be used. end process_name; 9/15/2020 Veton Këpuska 6

VHDL – Memory Example library IEEE; use IEEE. std_logic_1164. all; use WORK. std_logic_arith. all ; entity memory is port (address, write_data: in std_logic_vector(31 downto 0); Mem. Write, Mem. Read: in std_logic; read_data: out std_logic_vector(31 downto 0) end memory; architecture memory_func of memory is type mem_array is array(0 to 7) of std_logic_vector(31 downto 0); begin -- for architecture mem_process: process (address, write_data) variable data_mem: mem_array : = ( to_stdlogicvector(X” 00000000”), to_stdlogicvector(X” 00000000”), to_stdlogicvector(X” 0000”)); variable addr: integer; begin -- for process -- the following conversion function is in WORK. std_logic_arith package addr : = to_integer (address (2 downto 0)); if Mem. Write = ‘ 1’ then data_mem(addr) : = write_data; elsif Mem. Read = ‘ 1’ then read_data <= data_mem(addr) after 10 ns; end if; end process mem_process; end memory_func; 9/15/2020 Veton Këpuska 7

VHDL – Process Construct u Some important remarks to be noted: n n n 9/15/2020 All standard data type may be used. Variable assignment, using “: =“ operator, takes effect immediately. The value of a variable is visible to all following statements within that same process. Control flow within a process is strictly sequential and is altered only by constructs such as if-then-else and loop. Additional distinguishing feature of VHDL process is that assignments can be made to signals declared external to the process. The statements within a process are executed sequentially and are referred to as sequential statements. Veton Këpuska 8

VHDL – Process Construct u u CSA statements are executed when an event occurs on a signal on its right hand side. n When a process gets executed? Similarly, process gets executed when an event takes place on any of the signals on its input list. This list is thus referred to as sensitivity list. n Once a process gets started it executes in zero (simulated) time. n It can generate a new set of events on output signals, which in turn may trigger a number of processes and/or CSAs associated with them. n Note: VHDL CSAs are special (and less capable) processes. 9/15/2020 Veton Këpuska 9

Programming Constructs u Syntax of VHDL if statements: n n sequentialstatement elsif boolean-expression then sequentialstatement … elsif boolean-expression then sequentialstatement else sequentialstatement end if; if boolean-expression then sequentialstatement end if; n if boolean-expression then sequentialstatement else sequentialstatement end if; 9/15/2020 if boolean-expression then Veton Këpuska 10

Programming Constructs u Syntax of Case Statement case expression is when choices => sequential-statement; … when choices => sequential-statement; end case; 9/15/2020 Veton Këpuska 11

Programming Constructs u Concurrent Processes and the Case Statement library IEEE; use IEEE. std_logic_1164. all; entity half_adder is port (a, b: in std_logic; sum, carry: out std_logic end half_adder; architecture half_adder_func of half_adder is begin sum_process: process(a, b) begin if (a=b) then sum <= ‘ 0’ after 5 ns; else sum <= (a or b) after 5 ns; endif end process sum_process; carry_process: process(a, b) begin case a is when ‘ 0’ => carry <= a after 5 ns; when ‘ 1’ => carry <= b after 5 ns; when others => carry <= ‘X’ after 5 ns; end case; end process; end half_adder_func; 9/15/2020 Veton Këpuska 12

Programming Constructs u Loop construct while boolean-expression loop sequential-statement; … sequential-statement; end loop; u For construct for boolean-expression in range loop sequential-statement; … sequential-statement; end loop; 9/15/2020 Veton Këpuska 13

Example of the use of the loop constructs u Long multiplication using base 2 arithmetic. n Successive addition is simple for binary representation of numbers: u The multiplicand is added once or not added at all for each multiplier bit. 0110 X 0101 -----0110 + 0000 + 0110 +0000 -----0011110 9/15/2020 Veton Këpuska 14

Long multiplication using base 2 arithmetic. Multiplicand MD 0110 AC 0000 + + + 9/15/2020 MQ Multiplier |0101 0110 |0101 ADD 0011 0|010 SHIFT + 0000 0011 0|010 ADD 0001 10|01 SHIFT 0111 10|01 ADD 0011 110|0 SHIFT 0000 0011 110|0 ADD 0001 1110| SHIFT 0110 Veton Këpuska 15

Example of the use of the loop constructs library IEEE; use IEEE. std_logic_1164. all; use WORK. std_logic_arith. all; multiplicant_reregister : = multiplicant; product_register(63 downto 0) : = x’ 0000’& multiplier; --- repeated shift-and-add loop -for index in 1 to 32 loop if product_register(0) = ‘ 1’ then product_register (63 downto 32) : = product_register (63 downto 32)+multiplicant_register (31 downto 0); end if; entity mult 32 is port (multiplicant, multiplier: in std_logic_vector(31 downto 0); product: out std_logic_vector(63 downto 0) end mult 32; architecture mult 32_func of mult 32 is constant module_delay: Time : = 10 ns; begin -- architecture mult_process: process (multiplicand, multiplier) variable product_register: std_logic_vector(63 downto 0) : = x’ 00000000’; variable product_register: std_logic_vector(31 downto 0) : = x’ 0000’; begin -- process 9/15/2020 --perform right shift with zero fill product_register (63 downto 0) : = ‘ 0’ & product_register (63 downto 1); end loop; -- write result to output port product <= product_register after module_delay; end process mult_process; end mult 32_func; Veton Këpuska 16

More on Processes u Upon initialization all processes are executed once. Thereafter processes are executed in a data-driven manner: n n u All of the ports of the entity and the signals declared within an architecture are visible within a process: this means that they can be read or assigned values from within a process. n u activated by events on signals in the sensitivity list of the process, or by waiting for the occurrence of specific event using the wait statement. The process may read or write any of the signals declared in the architecture or any of the ports on the entity. This feature implies that a process (e. g. , A) may trigger execution of another process (e. g. , B) by changing the state of a signal which is in the sensitivity list of this other process (B). In turn the process B may change the state of a signal that triggers the event that executes the process A. n 9/15/2020 This is powerful mechanism that supports process communication. Veton Këpuska 17

Example of communicating process model of a full adder library IEEE; use IEEE. std_logic_1164. all; HA 2: process (s 1, c_in) -- process describing the second half adder begin s 1 <= (s 1 xor c_in) after delay; s 2 <= (s 1 and c_in) after delay; end process HA 2; entity full_adder is port (in 1, in 2, c_in: in std_logic; sum, c_out: out std_logic end full_adder; architecture full_adder_func of full_adder is signal s 1, s 2, s 3: std_logic; constant delay : Time : = 5 ns; begin HA 1: process (in 1, in 2) -- process describing the first half adder begin s 1 <= (in 1 xor in 2) after delay; s 2 <= (in 1 and in 2) after delay; end process HA 1; 9/15/2020 OR 1: process (s 2, s 3) -- process describing two input-or gate begin c_out <= (s 2 xor s 3) after delay; end process OR 1; end full_adder_func; Veton Këpuska 18

The Wait Statement u Presented examples describe behavior of models that is data-driven: n n 9/15/2020 Events on the input signals initiated execution of processes. Processes are suspended until next event on a signal defined it its sensitivity list. Fits well with the behavior of real combinational logic circuits. Fails to address behavior when circuits compute outputs only at specific point in time independent of events on the inputs. Veton Këpuska 19

The Wait Statement u u More specifically: in synchronous sequential circuts, the clock signal determines when the outputs may change or when inputs are read. Such behavior requires us to be able to specify in a more general mannaer the conditions under which the circuit outputs must be (re-)computed. In VHDL context, this means that there should be mechanisms in the language that in more general way allow specifications when a process is executed or suspended pending the occurrence of an event or events. This capability is provided in VHDL by wait statement. 9/15/2020 Veton Këpuska 20

The Wait Statement u Forms of wait statements: n n n 9/15/2020 wait for time-expression u Causes suspension of the process for a period of time given by time-expression: u wait for 20 ns; wait on signal u Process suspends execution until an event occurs on one or more signals in a group of signals: u wait on clk, reset, satus; wait until condition u Process is suspended until condition evaluates to a Boolean value (TRUE or FALSE). Veton Këpuska 21

The Wait Statement u u Wait statements provide mechanisms that allow construction of models where a process is suspended at multiple points within the process and not just at the beginning (as provided by sensitivity list). Example of Positive Edge-Triggered D Flip-Flop. 9/15/2020 Veton Këpuska 22

Positive Edge-Triggered D Flip-Flop u D Flip-Flop samples its D input on the rising/falling edge of the clock signal. Its input value is transferred to output at these specific and discrete points in time. 9/15/2020 S R Clk D Q Qbar 1 0 X X 1 0 0 1 X X 0 1 0 0 R 1 1 0 0 0 R 0 0 1 1 1 X X ? ? Veton Këpuska 23

D Flip-Flop with Asynchronous Set and Reset inputs library IEEE; use IEEE. std_logic_1164. all; entity asynch_dff is port (R, S, D, Clk: in std_logic; Q, Qbar: out std_logic end asynch_dff; architecture asynch_dff _func of asynch_dff is begin Dff_process: process (R, S, Clk) begin 9/15/2020 if (R = ‘ 1’) then Q <= ‘ 0’ after 5 ns; Qbar <= ‘ 1’ after 5 ns; elsif (S = ‘ 1’) then Q <= ‘ 1’ after 5 ns; Qbar <= ‘ 0’ after 5 ns; elsif (Clk’event and Clk=‘ 1’) then Q <= D after 5 ns; Qbar <= (not D) after 5 ns; endif; end process Dff_process; end asynch_dff_func; Veton Këpuska 24

Example of Asynchronous Communication u u RQ – request signal ACK – acknowledgment transmit_data Transmit data signal u 4 -phase handshake Following example illustrates n n 9/15/2020 The use of wait statement to control asynchronous communication between processes. The ability to suspend the execution of a process at multiple points within the VHDL code. Veton Këpuska 25

Example of Asynchronous Communication library IEEE; use IEEE. std_logic_1164. all ; entity handshake is port (input_data: in std_logic_vector(31 downto 0); end handshake; architecture handshake _func of handshake is signal transmit_data: std_logic_vector(31 downto 0); signal RQ, ACK: std_logic; begin producer: process begin -- wait until input data becomes available wait until input_data’event; -- provide data as producer transmit_data <= input_data; RQ <= ‘ 1’; wait until ACK = ‘ 1’; RQ <= ‘ 0’; wait until ACK = ‘ 0’; end process producer; consumer: process variable receive_data: std_logic_vector(31 downto 0); begin -- wait until producer makes the data available wait until RQ = ‘ 1’; receive_data : = transmit_data; -- read the data transmit_data <= input_data; ACK <= ‘ 1’; wait until RQ = ‘ 0’; ACK <= ‘ 0’; end process consumer; end handshake _func; 9/15/2020 Veton Këpuska 26

Attributes u D flip-flop example introduced the idea of an attribute of a signal. Attributes can be used to return various types of information about the signal. n Example: u u Determining if an event has occurred, Amount of time that has elapsed since the last event occurred on the signal: n Clk’last_event etc. In effect, when simulator executes the above statement a function call occurs that checks this property. This function returns the time since the last event occurred on signal clk. Such attributes are referred to as function attributes. 9/15/2020 Veton Këpuska 27

Some useful Function Attributes Function attribute Function signal_name’event Function returning a Boolean signifying a change in value on this signal_name’active Function returning a Boolean signifying an assignment made to this signal. This assignment may not be a new value. signal_name’last_event Function returning the time since the last event on this signal_name’last_active Function returning the time since the signal was last active. signal_name’last_value Function returning the previous value of this signal. 9/15/2020 Veton Këpuska 28

Attributes u u There are numerous other classes of attributes. Only one additional one will be described in this section: value attribute. These attributes return values. 9/15/2020 Veton Këpuska 29

Some useful Value Attributes Value attribute Value scalar_name’left Returns the left most value of scalar_name in its defined range. scalar_name’right Returns the right most value of scalar_name in its defined range. scalar_name’high Returns the highest value of scalar_name in its range. scalar_name’low Returns the lowest value of scalar_name in its range. scalar_name’ascending Returns true if scalar_name has an ascending range of values. array_name’length Returns the number of elements in the array_name. 9/15/2020 Veton Këpuska 30

Attributes u Example 1: Memory model described earlier contains the definition of a new type as follows: type mem_array is array(0 to 7) of std_logic_vector(31 downto 0); n n n 9/15/2020 mem_array’left = 0; mem_array’ascending = true; mem_array’length = 8; Veton Këpuska 31

Attributes u Example 2: When describing models of state machines it is useful to have the following data type (enumerated) defined: type state_type is (state 0, state 1, state 2, state 3); n n 9/15/2020 state_type’left = state 0; state_type’right = state 3; Veton Këpuska 32

Attributes u Example 3: A very useful attribute of arrays is the range attribute. Consider a loop that scans all of the elements in an array value_array. The index range is returned by the value_array’range: for i in value_array’range loop … my_var : = value_array(i); … end loop; 9/15/2020 Veton Këpuska 33

Generating Clocks and Periodic Waveforms u u Wait statements provide the programmer with explicit control over the reactivation of processes. Thus they can be used for generating periodic waveforms as shown in following example. Example of Generating Periodic Waveforms: n We have seen previously that we can assign to signals several future events as in this example: signal <= ‘ 0’, ‘ 1’ after 10 ns, ‘ 0’ after 20 ns, ‘ 1’ after 40 ns; n n 9/15/2020 This signal can be used within a process to be executed repeatedly thus producing a periodic waveform as presented in the next slide. Note that in VHDL upon initialization of the model all processes are executed. Veton Këpuska 34

Generating Clocks and Periodic Waveforms library IEEE; use IEEE. std_logic_1164. all; entity periodic is port (Z: out std_logic); end periodic; architecture periodic_func of periodic is begin process begin Z <= ‘ 0’, ‘ 1’ after 10 ns, ‘ 0’ after 20 ns, ‘ 1’ after 40 ns; wait for 50 ns; end process; end periodic_func; 9/15/2020 Veton Këpuska 35

Generating Clocks and Periodic Waveforms u Example of a Two-Phase Clock: Following VHDL code depicts an example of generation of nonoverlapping clocks and reset pulses. 9/15/2020 Veton Këpuska 36

Generating Clocks and Periodic Waveforms library IEEE; use IEEE. std_logic_1164. all; u entity two_phase is port (phi 1, phi 2, reset: out std_logic); end two_phase; Two phase nonoverlapping clocks architecture two_phase_func of two_phase is begin reset_process: reset <= ‘ 1’, ‘ 0’ after 10 ns; clock_process: process begin phi 1 <= ‘ 1’, ‘ 0’ after 10 ns; phi 2 <= ‘ 0’, ‘ 1’ after 12 ns, ‘ 0’ after 18 ns; wait for 20 ns; end process clock_process; end two_phase_func; 9/15/2020 Veton Këpuska 37

Modeling State Machines u The examples described up to now used only combinational and sequential circuits in isolation. n Processes that model combinational circuits are sensitive to the inputs; and are activated whenever an event occurs on an input signal. n Sequential devices on the other hand retain information stored in internal devices (e. g. , flip-flops and latches) and their outputs depends on their current state as well as current inputs. u u 9/15/2020 Sequential devices typically update their values at discrete points in time determined by a periodic signal (e. g. , clock). With finite number of storage elements, the number of unique states is finite and such circuits are referred to as finite state machines. Veton Këpuska 38

General Finite State Machine Inputs Combinational Outputs Logic Sequential Circuit Clk 9/15/2020 Veton Këpuska 39

Example of Finite State Machine u Convention: Input/Output 0/1 1/0 s 1 s 0 0/1 1/0 9/15/2020 Veton Këpuska 40

Example of Finite State Machine Synchronous Implementation library IEEE; use IEEE. std_logic_1164. all; entity state_machine is port (reset, clk, x: in std_logic; z: out std_logic; end state_machine; architecture state_machine _func of state_machine is type state_type is (state 0, state 1); signal state, next_state: state_type : = state 0; begin 9/15/2020 comb_process: process (state, x) begin case state is when state 0 => if x = ‘ 0’ then next_state <= state 1; z <= ‘ 1’; else next_state <= state 0; z <= ‘ 0’; endif when state 1 => if x = ‘ 1’ then next_state <= state 0; z <= ‘ 0’; else next_state <= state 1; z <= ‘ 1’; endif end case; end process comb_process; Veton Këpuska 41

Example of Finite State Machine (cont. ) clk_process: process begin -- wait until raising edge wait until (clk’event and clk = ‘ 1’); -- check for reset if reset = ‘ 1’ then state <= state_type’left; else state <= next_state; end if; end process clk_process; end state_machine_func; 9/15/2020 Veton Këpuska 42

Example of Finite State Machine Asynchronous Implementation library IEEE; use IEEE. std_logic_1164. all; entity state_machine is port (reset, clk, x: in std_logic; z: out std_logic; end state_machine; architecture state_machine _func of state_machine is type state_type is (state 0, state 1); signal state, next_state: state_type : = state 0; begin 9/15/2020 output_process: process (state, x) begin case state is when state 0 => if x = ‘ 1’ then z <= ‘ 0’; else z <= ‘ 1’; endif when state 1 => if x = ‘ 1’ then z <= ‘ 0’; else z <= ‘ 1’; endif end case; end process output_process; Veton Këpuska 43

Example of Finite State Machine (cont. ) next_state_process: process begin -- set next_state depending upon -- the current state and input signal case state is when state 0 => if x = ‘ 1’ then next_state <= state 0; else next_state <= state 1; endif when state 1 => if x = ‘ 1’ then next_state <= state 0; else next_state <= state 1; endif end case; end process next_state_process; 9/15/2020 clk_process: process begin -- wait until raising edge wait until (clk’evnet and clk = ‘ 1’); -- check for reset if reset = ‘ 1’ then state <= state_type’left; else state <= next_state; end if; end process clk_process; end state_machine_func; Veton Këpuska 44

Digression on Finite State Machines u u The most general model of sequential circuit has inputs, outputs and internal states. Two types of models are distinguished based on the way the output is generated: n n u u Mealy model and Moore model In the Mealy model the output is a function of both the present state and the input. In the Moore model the output is a function of present state only. 9/15/2020 Veton Këpuska 45