Digital Systems Computer Architecture Session for Digital Systems

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Digital Systems: Computer Architecture Session for “Digital Systems: Computers and Communications” A Fairfield University

Digital Systems: Computer Architecture Session for “Digital Systems: Computers and Communications” A Fairfield University E-Course Powered by Learn. Linc 9/24/2021 Digital Systems: Computers and Communications 1

Module: Digital Systems (in two parts) • Texts: – “Computers, ” Capron, Benjamin Cummings,

Module: Digital Systems (in two parts) • Texts: – “Computers, ” Capron, Benjamin Cummings, 1996, ISBN 08053 -0662 -5 “Telecommunications, ” Blyth, Mc. Graw-Hill, 1990, ISBN 0 -02680841 -2 “Understanding Telephone Electronics, ” Bigelow, Newnes, 1997, ISBN 0 -7506 -9944 – – • References: – – • Electronics Tutorial (Thanks to Alex Pounds) Electronics Tutorial (Thanks to Mark Sokos) Part 9 – Computers – • 5 on-line sessions plus one lab Part 10 – Digital Communications – • 5 on-line sessions plus one lab Mastery Test part 5 follows this Module 9/24/2021 Digital Systems: Computers and Communications 2

Digital Systems: Topics • Computer Architecture – – Memory: ROM, RAM, Cache, Error Checking

Digital Systems: Topics • Computer Architecture – – Memory: ROM, RAM, Cache, Error Checking CPU and Program Control Part 9 Secondary Storage: Floppy, Hard Drive, CD / DVD I/O (Human: Video, Keyboard, & Pointer) • Digital I/O: Serial, Parallel, IDE, USB. Fire. Wire, SCSI • Serial I/O: RS 232 • Modems Part 10 – Telephone: Modulation and Data compression – Cable and DSL • Telephony Digital Transmission • Packet Transmission • Fiber Optics: SONET 9/24/2021 Digital Systems: Computers and Communications 3

Section 9 Schedule Session 9 a (5/26 – Holiday) 05/21 Introduction: Computer Overview Capron:

Section 9 Schedule Session 9 a (5/26 – Holiday) 05/21 Introduction: Computer Overview Capron: Ch 1; Notes Session 9 b 05/28 The Central Processing Capron: Ch 2; Unit (CPU) Session 9 c 06/02 I/O Capron: Ch 3; Session 9 d 06/04 Data Storage Capron: Ch 4; Session 9 e 06/09 Digital I/O: Serial, Parallel, IDE, SCSI, USB, and Firewire Bigelow: pp. 285 -288, 301 -305; Notes Session 9 f 06/11 Review for Quiz 9 (Lab - 06/14, Sat. ) (Quiz 9 due 06/15) Session 9 g (6/18 – no class) 9/24/2021 06/16 Quiz Results Digital Systems: Computers and Communications 4

Computer Architecture 9/24/2021 Digital Systems: Computers and Communications 5

Computer Architecture 9/24/2021 Digital Systems: Computers and Communications 5

Computer Architecture (2) • CPU – Control Unit – ALU – Busses • Data

Computer Architecture (2) • CPU – Control Unit – ALU – Busses • Data • Address • Control (buss operation) • • Memory Interrupts DMA Parallel and Serial I/O 9/24/2021 Digital Systems: Computers and Communications 6

Central Processing Unit • Control Unit – Sequential control of operations – Program Memory

Central Processing Unit • Control Unit – Sequential control of operations – Program Memory determines sequence • Register: Fast temporary Data storage • Arithmetic Logic Unit (ALU) – Fixed Point • 18. 75 Decimal • 0010010. 1100 12 -bit Binary (1 sign bit) Control Unit Register ALU – Floating Point • 0. 1875*102 Decimal • 00001100*20010 12 -bit Binary (2 sign bits) 9/24/2021 Digital Systems: Computers and Communications 7

Memory • DRAM SIMM – Dynamic RAM • Low Power • Refresh – Single

Memory • DRAM SIMM – Dynamic RAM • Low Power • Refresh – Single Inline Multi-Chip Module 9/24/2021 Digital Systems: Computers and Communications 8

Interrupts • Allows software multi-tasking • Operating system (Windows, Linux, etc. ) – Looks

Interrupts • Allows software multi-tasking • Operating system (Windows, Linux, etc. ) – Looks for interrupt flag • Hardware: – Peripheral – Timing • Software – Sets aside current task • Saves all “State” information for the current task • Restores “State” information for new task and runs it for a limited time 9/24/2021 Digital Systems: Computers and Communications 9

Direct Memory Access (DMA) • Fast add-in card and memory communications – Hard Disk

Direct Memory Access (DMA) • Fast add-in card and memory communications – Hard Disk Storage – High Speed I/O • Bypasses CPU – CPU defines block transfer – DMA controller manages transfer 9/24/2021 Digital Systems: Computers and Communications 10

Serial and Parallel I/O DB-25 Centronics 36 pin male 9/24/2021 DB-9 Centronics 34 pin

Serial and Parallel I/O DB-25 Centronics 36 pin male 9/24/2021 DB-9 Centronics 34 pin female Digital Systems: Computers and Communications 11

PC Add-In Hardware: Peripherals • ISA: Industry Standard Architecture (old) – Original IBM PC

PC Add-In Hardware: Peripherals • ISA: Industry Standard Architecture (old) – Original IBM PC (Cloned) – PS 2 (32 -bit IBM) – VESA & EISA (Clone 32 -bit) • PCI: PC Interface (Current Standard) • PCMCIA (PC Card: Portable Standard) 9/24/2021 Digital Systems: Computers and Communications 12

Universal Serial Bus • New Standard Peripheral Connection System CPU Memory – Serial Data

Universal Serial Bus • New Standard Peripheral Connection System CPU Memory – Serial Data • USB 1: 12 Mbit/Sec • USB 2: 400 Mbit/sec – Tree Topology (Hubs) – Limited DC Power to USB Peripherals (Use Auxiliary Bricks) 9/24/2021 Computer BUS USB Controller Serial Interface Transceiver Digital Systems: Computers and Communications HUB Serial Ports 13

Section 9 Schedule Session 9 a (5/26 – Holiday) 05/21 Introduction: Computer Capron: Ch

Section 9 Schedule Session 9 a (5/26 – Holiday) 05/21 Introduction: Computer Capron: Ch 1; Overview Notes Session 9 b 05/28 The CPU - Central Processing Unit Capron: Ch 2; Session 9 c 06/02 I/O Capron: Ch 3; Session 9 d 06/04 Data Storage Capron: Ch 4; Session 9 e 06/09 Digital I/O: Serial, Parallel, IDE, SCSI, USB, and Firewire Bigelow: pp. 285 -288, 301 -305; Notes Session 9 f 06/11 Review for Quiz 9 (Lab - 06/14, Sat. ) (Quiz 9 due 06/15) Session 9 g (6/18 – no class) 9/24/2021 06/16 Quiz Results Digital Systems: Computers and Communications 14

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