Digital System Design Verilog HDL Basic Concepts 2005

Digital System Design Verilog® HDL Basic Concepts 2005 Verilog HDL Maziar Goudarzi

Today program l Lexical Conventions l Data Types l System Tasks and Compiler Directives 2005 Verilog HDL 2

Lexical Conventions l Very similar to C ¡ ¡ ¡ Verilog is case-sensitive All keywords are in lowercase A Verilog program is a string of tokens l l l l 2005 Whitespace Comments Delimiters Numbers Strings Identifiers Keywords Verilog HDL 3

Lexical Conventions (cont’d) l Whitespace ¡ ¡ ¡ l Blank space (b) Tab (t) Newline (n) Comments ¡ Used for readability and documentation Just like C: /* /* be on // single line comment l /* multi-line comment */ Nested comments like this */ may not acceptable (depends Verilog compiler) */ ¡ l Whitespace is ignored in Verilog except ¡ ¡ 2005 l In strings When separating tokens Verilog HDL 4

Lexical Conventions (cont’d) l Operators ¡ Unary a = ~b; ¡ Binary a = b && c; ¡ Ternary a = b ? c : d; // the only ternary operator 2005 Verilog HDL 5

Lexical Conventions (cont’d) l Number Specification ¡ Sized numbers ¡ Unsized numbers ¡ Unknown and high-impedance values ¡ Negative numbers 2005 Verilog HDL 6

Lexical Conventions (cont’d) l Sized numbers ¡ l General syntax: <size>’<base><number> l l ¡ <size> number of bits (in decimal) <number> is the number in radix <base> : • • Unsized numbers d or D for decimal (radix 10) b or B for binary (radix 2) o or O for octal (radix 8) h or H for hexadecimal (radix 16) ¡ ¡ Default base is decimal Default size is at least 32 (depends on Verilog compiler) Examples l l l 23232 ’habc ’o 234 Examples: • 4’b 1111 • 12’habc • 16’d 255 2005 Verilog HDL 7

Lexical Conventions (cont’d) l X or Z values ¡ Unknown value: lowercase x l ¡ High-impedance value: lowercase z l ¡ 4 bits in hex, 3 bits in octal, 1 bit in binary Examples l l l ¡ 4 bits in hex, 3 bits in octal, 1 bit in binary 12’h 13 x 6’hx 32’bz Extending the most-significant part l Applied when <size> is bigger than the specified value • Filled with x if the specified MSB is x • Filled with z if the specified MSB is z • Zero-extended otherwise l Examples: • 6’hx 2005 Verilog HDL 8

Lexical Conventions (cont’d) l Negative numbers ¡ ¡ Put the sign before the <size> Examples: l l ¡ l // illegal Two’s complement is used to store the value Underscore character and question marks ¡ Use ‘_’ to improve readability l l ¡ 12’b 1111_0000_1010 Not allowed as the first character ‘? ’ is the same as ‘z’ (only regarding numbers) l 2005 -6’d 3 4’d-2 4’b 10? ? // the same as 4’b 10 zz Verilog HDL 9

Lexical Conventions (cont’d) l Strings ¡ ¡ As in C, use double-quotes Examples: l l Identifiers and keywords ¡ identifiers: alphanumeric characters, ‘_’, and ‘$’ l l ¡ ¡ Should start with an alphabetic character or ‘_’ Only system tasks can start with ‘$’ Keywords: identifiers reserved by Verilog Examples: l l 2005 “Hello world!” “a / b” “texttcolumn 1bcolumn 2n” reg value; input clk; Verilog HDL 10

Lexical Conventions (cont’d) l Escaped identifiers ¡ ¡ ¡ 2005 Start with ‘’ End with whitespace (space, tab, newline) Can have any printable character between start and end The ‘’ and whitespace are not part of the identifier Examples: l a+b-c // a+b-c is the identifier l **my_name** // **my_name** is the identifier Used as name of modules Verilog HDL 11

Basic Concepts Data Types 2005 Verilog HDL

Data Types l l l l 2005 Value set and strengths Nets and Registers Vectors Integer, Real, and Time Register Data Types Arrays Memories Parameters Strings Verilog HDL 13

Value Set l Verilog concepts to model hardware circuits ¡ Value level ¡ Value strength l Used to accurately model • • 2005 Signal contention MOS devices Dynamic MOS Other low-level details Verilog HDL 14

Value Set Value level HW Condition 2005 Strength level Type 0 Logic zero, false supply Driving 1 Logic one, true strong Driving pull Driving large Storage weak Driving medium Storage small Storage highz High Impedance x Unknown z High imp. , floating Verilog HDL 15

Nets l Used to represent connections between HW elements ¡ ¡ l Values continuously driven on nets Fig. 3 -1 Keyword: wire ¡ Default: One-bit values l ¡ Default value: z l ¡ For trireg, default is x Examples l l l 2005 unless declared as vectors wire a; wire b, c; wire d=1’b 0; Verilog HDL 16

Registers l Registers represent data storage elements ¡ ¡ ¡ Retain value until next assignment NOTE: this is not a hardware register or flipflop Keyword: reg Default value: x Example: reg reset; initial begin reset = 1’b 1; #100 reset=1’b 0; end 2005 Verilog HDL 17

Vectors Net and register data types can be declared as vectors (multiple bit widths) l Syntax: l ¡ l wire/reg [msb_index : lsb_index] data_id; Example wire a; wire [7: 0] bus; wire [31: 0] bus. A, bus. B, bus. C; reg clock; reg [0: 40] virtual_addr; 2005 Verilog HDL 18

Vectors (cont’d) l Consider wire [7: 0] bus; wire [31: 0] bus. A, bus. B, bus. C; reg [0: 40] virtual_addr; l Access to bits or parts of a vector is possible: bus. A[7] bus[2: 0] // three least-significant bits of bus // bus[0: 2] is illegal. virtual_addr[0: 1] /* two most-significant bits * of virtual_addr */ 2005 Verilog HDL 19

Integer, Real, and Time Register Data Types l Integer ¡ ¡ Keyword: integer Very similar to a vector of reg l l ¡ integer variables are signed numbers reg vectors are unsigned numbers Bit width: implementation-dependent (at least 32 -bits) l Designer can also specify a width: integer [7: 0] tmp; ¡ Examples: integer counter; initial counter = -1; 2005 Verilog HDL 20

Integer, Real, and Time Register Data Types (cont’d) l Real ¡ ¡ Keyword: real Values: l l l ¡ ¡ Default value: 0 Decimal notation: 12. 24 Scientific notation: 3 e 6 (=3 x 106) Cannot have range declaration Example: real delta; initial begin delta=4 e 10; delta=2. 13; end integer i; initial i = delta; // i gets the value 2 (rounded value of 2. 13) 2005 Verilog HDL 21

Integer, Real, and Time Register Data Types (cont’d) l Time ¡ Used to store values of simulation time ¡ Keyword: time ¡ Bit width: implementation-dependent (at least 64) ¡ $time system function gives current simulation time ¡ Example: time save_sim_time; initial save_sim_time = $time; 2005 Verilog HDL 22

Arrays l l Only one-dimensional arrays supported Allowed for reg, integer, time ¡ l Not allowed for real data type Syntax: <data_type> <var_name>[start_idx : end_idx]; l Examples: integer count[0: 7]; reg bool[31: 0]; time chk_point[1: 100]; reg [4: 0] port_id[0: 7]; integer matrix[4: 0]; // illegal count[5] chk_point[100] port_id[3] l 2005 Note the difference between vectors and arrays Verilog HDL 23

Memories RAM, ROM, and register-files used many times in digital systems l Memory = array of registers in Verilog l Word = an element of the array l ¡ l Can be one or more bits Examples: reg membit[0: 1023]; reg [7: 0] membyte[0: 1023]; membyte[511] l Note the difference (as in arrays): reg membit[0: 127]; reg [0: 127] register; 2005 Verilog HDL 24

Parameters l Similar to const in C ¡ l But can be overridden for each module at compile-time Syntax: parameter <const_id>=<value>; l Gives flexibility ¡ l Allows to customize the module Example: parameter port_id=5; parameter cache_line_width=256; parameter bus_width=8; wire [bus_width-1: 0] bus; 2005 Verilog HDL 25

Strings are stored in reg variables. l 8 -bits required per character l The string is stored from the least-significant part to the most-significant part of the reg variable l Example: l reg [8*18: 1] string_value; initial string_value = “Hello World!”; l Escaped characters ¡ ¡ ¡ 2005 n: newline %%: % ”: “ t: tab \: ooo: character number in octal Verilog HDL 26

Basic Concepts System Tasks and Compiler Directives 2005 Verilog HDL

System Tasks l System Tasks: standard routine operations provided by Verilog ¡ Displaying on screen, monitoring values, stopping and finishing simulation, etc. l All 2005 start with $ Verilog HDL 28

System Tasks (cont’d) l $display: displays values of variables, strings, expressions. ¡ ¡ Syntax: $display(p 1, p 2, p 3, …, pn); p 1, …, pn can be quoted string, variable, or expression Adds a new-line after displaying pn by default Format specifiers: l l l 2005 %d, %b, %h, %o: display variable respectively in decimal, binary, hex, octal %c, %s: display character, string %e, %f, %g: display real variable in scientific, decimal, or whichever smaller notation %v: display strength %t: display in current time format %m: display hierarchical name of this module Verilog HDL 29

System Tasks (cont’d) l $display examples: ¡ $display(“Hello Verilog World!”); Output: Hello Verilog World! ¡ $display($time); Output: 230 ¡ ¡ reg [0: 40] virtual_addr; $display(“At time %d virtual address is %h”, $time, virtual_addr); Output: At time 200 virtual address is 1 fe 000001 c 2005 Verilog HDL 30

System Tasks (cont’d) l l reg [4: 0] port_id; $display(“ID of the port is %b”, port_id); Output: ID of the port is 00101 l l reg [3: 0] bus; $display(“Bus value is %b”, bus); Output: Bus value is 10 xx l $display(“Hierarchical name of this module is %m”); Output: Hierarchical name of this module is top. p 1 l $display(“A n multiline string with a %% sign. ”); Output: A multiline string with a % sign. 2005 Verilog HDL 31

System Tasks (cont’d) $monitor: monitors a signal when its value changes l Syntax: $monitor(p 1, p 2, p 3, …, pn); l ¡ ¡ p 1, …, pn can be quoted string, variable, or signal names Format specifiers just as $display Continuously monitors the values of the specified variables or signals, and displays the entire list whenever any of them changes. $monitor needs to be invoked only once (unlike $display) l l l 2005 Only one $monitor (the latest one) can be active at any time $monitoroff to temporarily turn off monitoring $monitoron to turn monitoring on again Verilog HDL 32

System Tasks (cont’d) l $monitor Examples: initial begin $monitor($time, “Value of signals clock=%b, reset=%b”, clock, reset); end ¡ 2005 Output: 0 value of signals clock=0, reset=1 5 value of signals clock=1, reset=1 10 value of signals clock=0, reset=0 Verilog HDL 33

System Tasks (cont’d) l $stop: stops simulation ¡ ¡ Simulation enters interactive mode when reaching a $stop system task Most useful for debugging $finish: terminates simulation l Examples: l initial begin clock=0; reset=1; #100 $stop; #900 $finish; end 2005 Verilog HDL 34

Compiler Directives l General syntax: `<keyword> `define: similar to #define in C, used to define macros l `<macro_name> to use the macro defined by `define l Examples: l `define WORD_SIZE 32 `define S $stop `define WORD_REG reg [31: 0] `WORD_REG a_32_bit_reg; 2005 Verilog HDL 35

Compiler Directives (cont’d) `include: Similar to #include in C, includes entire contents of another file in your Verilog source file l Example: l `include header. v. . . <Verilog code in file design. v>. . . 2005 Verilog HDL 36

What we learned today l Basic concepts in Verilog ¡ l Verilog is very similar to C Various data types available in Verilog ¡ Verilog uses 4 -valued logic: 0, 1, x, z System tasks are Verilog statements used to request something from simulator l Compiler directives instruct the compiler to do something for us at compile-time l 2005 Verilog HDL 37

Other Notes l Course web-page ¡ http: //ce. sharif. edu/courses/84 -85/1/ce 223/ l Exercise 2 ¡ Chapter 3 exercises ¡ Due date: Next Sunday (Aban 8 th) 2005 Verilog HDL 38