Digital System Design Course Introduction Maziar Goudarzi Course

Digital System Design Course Introduction Maziar Goudarzi

Course Outline • Course contents – Verilog HDL® – Design Methodology – Programmable Logic Devices • Course timing – Will be put on the Courseware page • Teaching Assistants – As announced • Exercise classes – Sunday or Tuesday 12 -13, Place: TBA 2010 DSD 2

Textbook and References • Textbook – Samir Palnitkar, Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition, Prentice Hall PTR, 2003. – Zoran Salcic, Asim Smailagic, Digital System Design and Prototyping Using Field Programmable Logic and Hardware Description Languages, Kluwer Academic Publishers, 2002. • Other references – Pong P. Chu, FPGA Prototyping by Verilog Examples, Wiley, 2008. – J. Bhaskar, Verilog HDL Synthesis: A Practical Primer, Star Galaxy Publishing, 1998. – Chan, Mourad, Digital Design Using Field Programmable Gate Arrays, Prentice Hall PTR, 1994. – Verilog HDL, IEEE 1364 -2005 Standard, IEEE Computer Society, Design Automation Standards Committee, 2006. 2010 DSD 3

Evaluation • 50% or more Assignments and Course Project • 25% Midterm exam • 25% Final exam 2010 DSD 4

Digital System Design Introduction to Hardware Description Languages

Digital System • Digital vs. Analog 2010 DSD 6

Why HDL? Evolution of Logic Design • Early days – 10 s of logic gates 2010 DSD 7

Evolution of Logic Design (cont’d) �A decade later � 100 s of logic gates �Schematic design �Another decade later � 1000 s of logic gates �Structural Hardware Description Languages (HDL) �State of the art � 10, 000 s-1000, 000 s-10, 000 s logic gates �Behavioral and Register Transfer Level HDL 2010 DSD 8

Evolution of Logic Design (cont’d) HDL-based Design 2010 DSD 9

Why HDLs? • • SSI (Small Scale Integration) MSI (Medium Scale Integration) LSI (Large Scale Integration) VLSI (Very Large Scale Integration) • Important concepts – Simulation = check if design works fine – Synthesis = implement the design on real hardware 2010 DSD 10

HDL Requirements • • • 2010 Concurrency Timing and Delay Event-driven Design Hierarchy Implementation independence Readability (Documentation) DSD 11

Popular Levels of Abstraction Behavioral Data flow problem Structural Switch 2010 DSD 12

Popular Levels of Abstraction (cont’d) Behavioral Data flow problem Structural Switch 2010 DSD 13

Popular Levels of Abstraction (cont’d) Behavioral Data flow problem Structural Switch 2010 DSD 14

Popular Levels of Abstraction (cont’d) Behavioral Data flow problem Structural Switch 2010 DSD 15

HDL Examples �AHDL �Altera HDL �CDL: Computer Description Language � 1965 �ISPS: Instruction Set Processor Specification �AHPL: A Hardware Programming Language �Abel �Small designs such as state machines 2010 DSD 16

Verilog HDL � Verifying Logic � Phil Moorby from Gateway Design Automation in 1984 to 1987 (absorbed by Cadence) � Verilog-XL Simulator from GDA in 1986 � Synopsys synthesis tool in 1988 � In 1990 became open language, OVI (Open Verilog International) � IEEE standard 1995 � Similar to C � Fairly efficient and easy to write 2010 DSD 17

VHDL � VHSIC HDL: Very High Speed Integrated Circuit Hardware Description Language � DARPA workshop on VHSIC in 1981 � DARPA released requirement in 1983 � A language for hardware documentation � VHDL 7. 2 in 1985 � IEEE standard in 1987 � ANSI standard in 1988 � For RTL design VITAL added, � VITAL(VHDL Initiative Towards ASIC Library) � IEEE revised VHDL & VITAL in 1993 � Final review of standard in 2001 � Similar to Ada (emphasis on re-use and maintainability) � Very general, but verbose 2010 DSD 18

Hello World! VHDL vs. Verilog VHDL Verilog ---------------------- Design Name : hello_world --------------------- //--------------------------// This is my first Verilog Program // Design Name : hello_world // File Name : hello_world. v // Function : This program will print 'hello world‘ // Coder : Deepak //--------------------------- entity hello_world is end; architecture hello_world of hello_world is begin stimulus : process begin assert false report "Hello World By Deepak“ severity note; wait; end process stimulus; end hello_world; 2013 module hello_world ; initial begin $display ("Hello World by Deepak"); #10 $finish; endmodule // End of Module hello_world DSD Ref: www. asic-world. com 19

VHDL vs. Verilog • All abstraction levels • Designed for documentation • Ada based constructs • High level & system descriptor • No PLI 2010 • All abstraction levels • Designed for hardware design • C and Ada constructs • Gate & structural descriptor • Very powerful PLI DSD 20

VHDL vs. Verilog Behavioral VHDL Dataflow Structural & Gate Verilog Switch 2010 DSD 21

VHDL vs. Verilog VHDL, More popular in Europe � Verilog, In USA, Japan � 2010 DSD 22

Announcement 1. ﺍﻭﻟیﻦ ﺩﻭﺭﻩ کﺸﻮﺭی ﻣﺴﺎﺑﻘﻪ ﻃﺮﺍﺣی ﺳیﺴﺘﻤﻬﺎی ﺩیﺠیﺘﺎﻝ – ﻣﺴﺎﺑﻘﻪ ﺩﻭ ﺑیﻦ ﻃﺮﺣﻬﺎی ﺳﺨﺖ ﺍﻓﺰﺍﺭی – ﻣﺴﺎﺑﻘﻪ ﻃﺮﺍﺣی ﺷﺘﺎﺏ ﺩﻫﻨﺪﻩ ﺑﺮﺍی یک ﺍﻟگﻮﺭیﺘﻢ ﺭﻣﺰگﺬﺍﺭی http: //fpgasoc. ir 2. FPT’ 2013 Design Contest – Design hardware for a Game – Designs compete against one another in a live contest http: //lut. eee. u-ryukyu. ac. jp/dc 13/ 3. Model. Sim Getting Started class – – – 2013 Next Sunday (time and place to be announced) Software link will be provided Bring your laptop if any DSD 23