Digital Processing System Shuvra S Bhattacharyya Department of

Digital Processing System Shuvra S. Bhattacharyya Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies University of Maryland College Park MD 20742 ssb@eng. umd. edu, (301)405 -3638, http: //www. ece. umd. edu/~ssb/ With Neil Goldsman and Babis Papadopoulis Laboratory affilations: Digital Signal Processing Laboratory, VLSI Design Automation Laboratory, Embedded Systems Research Laboratory, Communications and Signal Processing Laboratory

Digital Processing Platform n Low power micro-controller n Small size for compact integration n Enables adaptation of node behavior with changing requirements, environmental characteristics, and network state n Enables experimentation with different algorithms and protocols n Enables use of energy saving processor modes and associated operating system functionality n Development of streamlined software implementations n Highly memory-constrained software implementations are required due to size and energy constraints n Leverage our previous work in synthesis of memory-efficient embedded software implementations n Employ formal programming models, and apply graph-theoretic analysis and optimization of program structure n Explore migration into ASIC or 3 D-integrated system University of Maryland at College Park Smart Dust Digital Processing,

Example of Software Structure Receiver No new data Low power sleep mode Periodic wake-up Check for new data Sensor Transmitter No Broadcast new data Yes Extract data Need to update neighbors? University of Maryland at College Park Fuse with prior data Smart Dust Digital Processing,

Protocol Set-up and System Configuration n Handshaking n Source channel coding n Integrate with transceiver to establish PLL timing n Establish error correction coding n Establish low-complexity decoding n Assign transmission power n Assign processing tasks to network nodes University of Maryland at College Park Smart Dust Digital Processing,

System-level Optimization Example: Task Assignment Algorithms n Need to balance communication and computation throughout the network n Develop models of power consumption in network nodes and communication links n Develop task graph models of overall network functionality n Develop algorithms to embed task graph algorithm specifications into the network Assign processing tasks to network nodes n Turn off idle nodes n Large design space n n Explore evolutionary algorithms to optimize task graph embeddings University of Maryland at College Park Smart Dust Digital Processing,

Evolutionary Algorithms Selection Phenotype space (Original search space) P(t+1) P(t) Decoding function Genetic operators Genotype space (Genetic representation) University of Maryland at College Park G(t+1) G(t) Smart Dust Digital Processing,

References: selected prior work related to embedded software optimization n N. K. Bambha, S. S. Bhattacharyya, J. Teich, and E. Zitzler. Systematic integration of parameterized local search in evolutionary algorithms. IEEE Transactions on Evolutionary Computation. To appear. n S. S. Bhattacharyya. Hardware/software co-synthesis of DSP systems. In Y. H. Hu, editor, Programmable Digital Signal Processors: Architecture, Programming, and Applications, pages 333 -378. Marcel Dekker, Inc. , 2002. n P. K. Murthy and S. S. Bhattacharyya. Shared buffer implementations of signal processing systems using lifetime analysis techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(2): 177 -198, February 2001. n S. S. Bhattacharyya, R. Leupers, and P. Marwedel. Software synthesis and code generation for DSP. IEEE Transactions on Circuits and Systems --- II: Analog and Digital Signal Processing, 47(9): 849 -875, September 2000. University of Maryland at College Park Smart Dust Digital Processing,