Digital LogicCNET 111 Chapter4 Combinational Logic Outline of

Digital Logic(CNET 111) Chapter-4 Combinational Logic

Outline of Chapter 4 4. 1 Introduction 4. 2 Combinational Circuits 4. 3 Binary Adder – Subs tractor 4. 4 Half Adder 4. 5 Full Adder 4. 6 Half Subtractor 4. 7 Full Subtractor 4. 8 Decoders 4. 9 Encoders 4. 10 Multiplexers

Objectives of Chapter-4 Ø In this chapter you will learn about combinational logic uses in Ø Digital circuit design. You will also come to know the importance in day to day life about Digital Systems. At the end of this chapter you will be able to answer the below questions which is in Text book exercise. What is combinational circuit? How to design a Half Adder/Subtractor circuit? How to design a Full Adder/Subtractor circuit? How to decoder circuit? How to design a Encoder circuit? How to design a Multiplexer circuit?

4. 1 Introduction Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. A combinational circuit performs an operation that can be specified logically by a set of Boolean functions.

Combinational Logic

4. 2 Combinational Circuit Combinational Logic: Output only depends on current input Sequential Logic: Output depends on current and previous inputs A combinational circuit consists of an interconnection of logic gates. Combinational logic gates react to the values of the signals at their inputs and produce the value of the output signal, transforming binary information from the given input data to a required output data. A block diagram of a combinational circuit is shown in Fig. 4. 1

4. 3 BINARY ADDER–SUBTRACTOR Digital computers perform a variety of information-processing tasks. Among the functions encountered are the various arithmetic operations. The most basic arithmetic operation is the addition of two binary digits. This simple addition consists of four possible elementary operations: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10 The first three operations produce a sum of one digit, but when both augend addend bits are equal to 1, the binary sum consists of two digits. The higher significant bit of this result is called a carry. When the augend addend numbers contain more significant digits, the carry obtained from the addition of two bits is added to the next higher order pair of significant bits.

BINARY ADDER–SUBTRACTOR A combinational circuit that performs the addition of two bits is called a half adder. One that performs the addition of three bits (two significant bits and a previous carry) is a full adder. Two half adders can be employed to implement a full adder. A binary adder–subtractor is a combinational circuit that performs the arithmetic operations of addition and subtraction with binary numbers. We will develop this circuit by means of a hierarchical design. The half adder design is carried out first, from which we develop the full adder.

4. 4 Half Adder Truth Table

Half Adder circuit

Full Adder Truth table

Full Adder S = xyz + xyz C = xy + xz + yz

Full Adder

Full Adder The Boolean expression for the Sum(S) and Carry(C) output is S=XY’Z’ +X’YZ’ + XYZ + X’Y’Z = Z’ (XY’+X’Y) + Z (XY + X’Y’) = Z’ (XY’ + X’Y) + Z (XY’ + X’Y)’ = Z (X Y) C= XY’Z + X’YZ + XYZ’+XYZ = XY’Z + X’YZ + XY(Z’+Z) = XY’Z + X’YZ + XY = Z(XY’ + X’Y) + XY = Z (X Y) + XY

Full Adder circuit with two Half Adder and one OR gate.

Half Subtractor Half subtractor accepts two binary digits as input (Minuend and Subtrahend) and produces two outputs, a Difference bit (Di) and Borrow bit (B 0).

Half Subtractor

Half Subtractor The difference (Di) output column of the truth table is an XOR operation. Di = A B The Boolean expression for the borrow (B 0) output is

Half Subtractor LOGIC DIAGRAM OF HALF SUBTRACTOR

FULL SUBTRACTOR The FS accepts three inputs including a borrow input (Bin) and produces a difference output (D) and a borrow output (B 0).

FULL SUBTRACTOR-Truth Table and Logic Symbol

FULL SUBTRACTOR Boolean Expressions for Full Subtractor D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin = A’(B’Bin + BBin’) + A(B’ Bin’ + BBin) = A’(B Bin) + A(B Bin)’ = A B Bin B 0 = A’B’Bin + A’BBin’ + A’BBin + ABBin = A’B’Bin + ABBin + A’B(Bin + Bin’) = Bin( A B)’ + A’B

FULL SUBTRACTOR Boolean Expressions for Full Subtractor Difference output of the FS can be given by D=A B Bin The borrow output of the FS can be derived by the truth table as follows.

FULL SUBTRACTOR LOGIC DIAGRAM FOR FULL SUBTRACTOR

Decoder A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. The decoders presented here are called n -to- m -line decoders, where m … 2 n. Their purpose is to generate the 2 n (or fewer) minterms of n input variables. Each combination of inputs will assert a unique output. The name decoder is also used in conjunction with other code converters, such as a BCD-to-sevensegment decoder. As an example, consider the three-to-eight-line decoder circuit of Fig. 4. 18.

Decoder

Decoder

Encoder An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code corresponding to the input value. An example of an encoder is the octal-to-binary encoder whose truth table is given in Table 4. 7. It has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary number. It is assumed that only one input has a value of 1 at any given time.

Encoder

Encoder the following Boolean output functions:

Encoder Octal to Binary Encoder Circuit

MULTIPLEXERS A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2 n input lines and n selection lines whose bit combinations determine which input is selected. A multiplexer is also called a data selector , since it selects one of many inputs and steers the binary information to the output line.

MULTIPLEXERS A two-to-one-line multiplexer connects one of two 1 -bit sources to a common destination, as shown in Fig. 4. 24 The circuit has two data input lines, one output line, and one selection line S Function Table of 2 -to-1 line MUX as: S Y 0 I 0 1 I 1 the Boolean output function as: Y = I 0 S’ + I 1 S

MULTIPLEXERS

MULTIPLEXERS Function Table of four-to-one- line MUX as: S 1 S 0 Y 0 0 I 0 0 1 I 1 1 0 I 2 1 1 I 3 the Boolean output function as: Y = I 0 S 0¯S 1¯ + I 1 S 0 S 1¯ + I 2 S 0¯S 1 + I 3 S 0 S 1

MULTIPLEXERS A four-to-one-line multiplexer is shown in Fig. 4. 25

EXAM – 2 DATE: 22 -11 -2017(2242) DATE: 26 -11 -2017(2238) DAY: WEDNESDAY(2242) & SUNDAY(2238) TIME: 2: 00 – 3: 00 PM & 1: 00 – 2: 00 PM MARKS: 10 MARKS SYLLABUS: CHAPTER – 3 & CHAPTER - 4