Digital Design Through Verilog Hardware Modeling 1 Overview

Digital Design Through Verilog Hardware Modeling 1

Overview Verilog modules Verilog primitives Structural descriptions Behavioral descriptions Hierarchical design Language conventions 2

Verilog Module Description of internal structure/function n n Implicit semantic of time associated with each data object/signal Implementation is hidden to outside world Communicate with outside through ports n Port list is optional Achieve hardware encapsulation module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule a b sum c_out_bar c_out 3

Behavioral Description module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; assign { c_out, sum } = a + b; // Continuous assignment endmodule Concatenation a b Add_half sum c_out 4

Module Instantiation Accomplished by entering n n Module name as a module item within a parent module Signal identifiers at appropriate ports Module instantiation needs a module identifier A module is never declared within another module The order of ports in instantiation usually matches the order in module declaration 5

Design a Full Adder sum. HA = a b c_out. HA = a • b sum. FA = a b c_in c_out. FA = a • b + b • c_in + a • c_in sum. FA = (a b) c_in c_out. FA = (a b) • c_in + a • b 6

Full Adder 2 Half Adders sum. HA = a b c_out. HA = a • b sum. FA = (a b) c_in c_out. FA = (a b) • c_in + a • b c_in a b Add_half a b (a b) c_in (a b) • c_in a • b (a b) • c_in + a • b 7

Full Adder in Verilog c_in a b Add_half w 1 a b w 2 a • b Add_half (a b) c_in w 3 (a b) • c_in sum c_out (a b) • c_in + a • b module Add_full ( sum, c_out, a, b, c_in ); // parent module input a, b, c_in; output c_out, sum; wire w 1, w 2, w 3; Module instance name Add_half M 1 ( w 1, w 2, a, b ); Add_half M 2 ( sum, w 3, w 1, c_in ); // child module or ( c_out, w 2, w 3 ); // primitive instantiation endmodule 8

Verilog Primitives Basic element to build a module, such as nand, nor, buf and not gates Never used stand-alone in design, must be within a module Pre-defined or user-defined Identifier (instance name) is optional Output is at left-most in port list Default delay = 0 9

Symmetric Delay Assignment module AOI_4 ( y, x 1, x 2, x 3, x 4 ); input x 1, x 2, x 3, x 4; x 1 output y; x 2 wire y 1, y 2; x 3 and #1 ( y 1, x 2 ); x 4 and #1 ( y 2, x 3, x 4 ); nor #1 ( y, y 1, y 2 ); endmodule y 1 y y 2 10

Asymmetric Delay Assignment module nand 1 ( O, A, B ); input A, B; Min delay output O; Typical delay nand ( O, A, B ); Max delay specify specparam T 01 = 1. 13: 3. 09: 7. 75; Falling time T 10 = 0. 93: 2. 50: 7. 34; ( A=>O ) = ( T 01, T 10 ); ( B=>O ) = ( T 01, T 10 ); endspecify Rising time endmodule 11

Smart Primitives module nand 3 ( O, A 1, A 2, A 3 ); input A 1, A 2, A 3; output O; nand ( O, A 1, A 2, A 3 ); endmodule Same primitive can be used to describe for any number of inputs This works for only pre-defined primitives, not UDP 12

Explicit Structural Descriptions module AOI_4 ( y, x 1, x 2, x 3, x 4 ); input x 1, x 2, x 3, x 4; output y; x 1 wire y 1, y 2; x 2 and #1 ( y 1, x 2 ); and #1 ( y 2, x 3, x 4 ); nor #1 ( y, y 1, y 2 ); endmodule x 3 x 4 y 1 y y 2 13

Implicit Structural Description module nand 2_RTL ( y, x 1, x 2 ); input x 1, x 2; output y; assign y = x 1 ~& x 2; endmodule Explicit continuous assignment module nand 2_RTL ( y, x 1, x 2 ); input x 1, x 2; output y; wire y = x 1 ~& x 2; endmodule Implicit continuous assignment Continuous assignment – Static binding between LHS and RHS No mechanism to eliminate or alter the binding 14

Multiple Instantiations module multiple_gates ( y 1, y 2, y 3, a 1, a 2, a 3, a 4 ); input a 1, a 2, a 3, a 4; output y 1, y 2, y 3; nand #1 G 1(y 1, a 2, a 3), (y 2, a 3, a 4), (y 3, a 1, a 4); endmodule The delay element #1 is effective for all instances 15

Multiple Assignments module multiple_gates ( y 1, y 2, y 3, a 1, a 2, a 3, a 4 ); input a 1, a 2, a 3, a 4; output y 1, y 2, y 3; assign #1 y 1 = a 1 ^ a 2, y 2 = a 2 | a 3, y 3 = a 1 + a 4; endmodule 16

Structural Connections By order By name Empty port module child( a, b, c ); … endmodule parent; wire u, v, w; child m 1( u, v, w ); child m 2(. c(w), . a(u), . b(v) ); child m 3( u, , w ); endmodule 17

Behavioral Descriptions: Data Flow module and 4( y, x ); input [3: 0] x; output y; assign y = & x; endmodule Flip_flop ( q, data_in, clk, rst ); input data_in, clk, rst; output q; reg q; always @ ( posedge clk ) begin if ( rst == 1) q = 0; else q = data_in; endmodule 18

Behavioral Descriptions: Algorithm-based module and 4_algo ( y, x ); input [3: 0] x; output y; reg y; integer k; always @ ( x ) begin: and_loop y = 1; for ( k = 0; k <= 3; k = k+1 ) if ( x[k] == 0 ) begin y = 0; disable and_loop; end endmodule x[0] or x[1] or x[2] or x[3] Optional name Enable “disable” 19

Description Styles Explicit structural Implicit structural n n Structural Explicit continuous assignment Implicit continuous assignment Data flow/RTL Algorithm-based Behavioral 20

Hierarchical Description M 2 c_in a M 1 sum Add_half c_out b Nested module instantiation to arbitrary depth Add_full M 1 xor M 2 Add_half nand not xor or Add_half nand not 21

Structured Design Methodology Design: top-down Verification: bottom-up 22

Arrays of Instances module flop_array(q, in, clk, rst); input [7: 0] in; input clk, rst; output [7: 0] q; Flip_flop M[7: 0] (q, in, clk, rst); endmodule rst in[7: 0] pipe[23: 16] q[7: 0] module pipeline(q, in, clk, rst ); input [7: 0] in; input clk, rst; clk output [7: 0] q; wire [23: 0] pipe; flop_array M[3: 0] ({q, pipe}, {pipe, in}, clk, rst); q[7: 0]pipe[23: 0], pipe[23: 0]in[7: 0] endmodule 23

Verilog for Synthesis module comp(lt, gt, eq, a 0, a 1, b 0, b 1); input a 0, a 1, b 0, b 1; output lt, gt, eq; wire w 1, w 2, w 3, w 4, w 5, w 6, w 7; or (lt, w 1, w 2, w 3); nor (gt, lt, eq); and (w 1, w 6, b 1); and (w 2, w 6, w 7, b 0); and (w 3, w 7, b 0, b 1); not (w 6, a 1); not (w 7, a 0); xnor (w 4, a 1, b 1); xnor (w 5, a 0, b 0); endmodule comp(lt, gt, eq, a, b); input [1: 0] a, b; output lt, gt, eq; assign it = ( a < b ); assign gt = ( a > b ); assign eq = ( a == b ); endmodule 24

Language Conventions Case sensitive Instance of a module must be named Keywords are lower-case Comments start with “//”, or blocked by “/* */” 25

Numbers in Verilog: Binary number : : = binary | octal | hex | decimal | real binary : : = [size] binary_base binary_digits binary_base : : = 'b | 'B binary_digits : : = x | X | z | Z | 0 | 1 Examples 'b 100 x 8'b 101 5'Bz // 4 -bit binary number, LSB unknown // 8 -bit binary number 0000 0101 // 5 -bit binary number zzzzz Automatic left padding rule If MSB is 0 or 1, pad with 0 If MSB is x or z, pad with x or z, respectively 26

Numbers: Octal and Hex number : : = binary | octal | hex | decimal | real octal : : = [size] octal_base octal_digits octal_base : : = 'o | 'O octal_digits : : = x | X | z | Z | 0 | 1 | … | 7 hex : : = [size] hex_base hex_digits hex_base : : = 'h | 'H hex_digits : : = x | X | … | 9 | a | A | … | f | F Size always means bits Base is only for value Examples 'h 837 F 8'HA 4'O 57 // 16 -bit binary, or 4 -digit hex // 8 -bit binary number 0000 1010 // 4 -bit binary number 1111 27

Numbers: Decimal number : : = binary | octal | hex | decimal | real decimal : : = [sign] unsigned_number | [size] decimal_base unsigned_number decimal_base : : = 'd | 'D Examples 'd-837 F 8'D 100 4'd 15 // wrong // 8 -bit binary number 0110 0100 // 4 -bit binary number 1111 28