Digital Design Principles and Practices Chapter 8 Sequential

Digital Design: Principles and Practices Chapter 8 Sequential Logic Design Practices

8. 4 Counters

Counter • The name counter is generally used for any clocked sequential circuit whose state diagram contains a single cycle, as shown in the next slide (Figure 8 -23). • The modulus of a counter is the number of states in the cycle. • A counter with m states is called a modulo-m counter, or divide-by-m counter. • A counter with a non-power-of-2 modulus has extra states that are not used in normal operation. 3

General Structure of a Counter State Diagram – A Single Cycle 4

8. 4. 1 Ripple Counters

A 4 -Bit Binary Ripple Counter 6

Ripple Counter • A T flip-flop changes state (toggles) on every rising edge of its clock input. • Thus, each bit of the counter toggles if and only if the immediately preceding bit changes from 1 to 0, it generates a carry to the next most significant bit. • Although a ripple counter requires fewer components than any other type of binary counter, it does so at a price – it is slower than any other type of binary counter. • In the worst case, when the most significant bit must change, the output is not valid until time n．t. TQ after the rising edge of CLK, where t. TQ is the propagation delay from input to output of a T flipflop. 7

Synchronous Serial Counter 8

Synchronous Serial Counter • CNTEN: Master count-enable signal • Each T flip-flop toggles if and only if CNTEN is asserted and all of the lower-order counter bits are 1. 9

Synchronous Parallel Counter 10

Synchronous Parallel Counter • Synchronous parallel counter is the fastest binary counter structure. 11

2 -Bit Asynchronous Counter (LSB) (MSB)

Asynchronous Counters • The clock input of an asynchronous counter is always connected only to the LSB flip-flop. • Asynchronous counters are also known as ripple counters.

3 -Bit Asynchronous Counter

Propagation Delay in 3 -Bit Counter

4 -Bit Asynchronous Counter

Asynchronous Decade Counter

Terms • Recycle Ø the transition of the counter from its final state back to its original state. • Modulus Ø the number of states Ø the maximum possible number of states (maximum modulus) of a counter is 2 n, where n is the number of flip-flops in the counter.

74 LS 93 (4 -Bit Asyn. Counter)

74 LS 93 (4 -Bit Asyn. Counter)

2 -Bit Synchronous Counter

2 -Bit Synchronous Counter

2 -Bit Synchronous Counter

3 -Bit Synchronous Counter

4 -Bit Synchronous Counter

4 -Bit Synchronous Decade Counter • J 0 = K 0 = 1 • • • J 1 = K 1 = Q 0 Q 3 J 2 = K 2 = Q 0 Q 1 J 3 = K 3 = Q 0 Q 1 Q 2 + Q 0 Q 3

4 -Bit Synchronous Decade Counter • J 0 = K 0 = 1 • • • J 1 = K 1 = Q 0 Q 3 J 2 = K 2 = Q 0 Q 1 J 3 = K 3 = Q 0 Q 1 Q 2 + Q 0 Q 3

The Johnson Counter

4 -bit Johnson Counter

4 -bit Johnson Counter

4 -bit Johnson Counter Clock Pulse Q 0 Q 1 Q 2 Q 3 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1

5 -bit Johnson Counter

5 -bit Johnson Counter

5 -bit Johnson Counter Clock Pulse Q 0 Q 1 Q 2 Q 3 Q 4 0 0 0 1 1 0 0 2 1 1 0 0 0 3 1 1 1 0 0 4 1 1 0 5 1 1 1 6 0 1 1 7 0 0 1 1 1 8 0 0 0 1 1 9 0 0 1

The Johnson Counter • In a Johnson counter, the complement of the output of the last flip-flop is connected back to the D input of the first flipflop. • A 4 -bit Johnson counter has 8 states (or bit patterns). • A 5 -bit Johnson counter has 10 states (or bit patterns). • In general, an n-bit Johnson counter will produce 2 n states.

The Ring Counter

The Ring Counter

The Ring Counter Clock Pulse Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 9 0 1 0 0 0 0 2 0 0 1 0 0 0 0 3 0 0 0 1 0 0 0 4 0 0 1 0 0 0 5 0 0 0 1 0 0 6 0 0 0 1 0 0 0 7 0 0 0 0 1 0 0 8 0 0 0 0 1 0 9 0 0 0 0 0 1

8. 5 Shift Registers

8. 5. 1 Shift-Register Structure

Shift Register • A shift register is an n-bit register with a provision for shifting its stored data by one bit position at each tick of the clock. • Shift Register Structures Ø Serial-in, serial-out Ø Serial-in, parallel-out Ø Parallel-in, serial-out Ø Parallel-in, parallel-out 41

Serial-In, Serial-Out Shift Register 42

Serial-In, Parallel-Out Shift Register 43

Parallel-In, Serial-Out Shift Register 44

Parallel-In, Parallel-Out Shift Register 45

Basic Shift Register Functions • Data Storage • Data Movement Ø Serial In / Serial Out Ø Serial In / Parallel Out Ø Parallel In / Serial Out Ø Parallel In / Parallel Out Ø Bi-directional

Shift Register - Data Storage

Shift Register - Data Movement

Serial In / Serial Out Shift Register With four stages, this shift register can store up to four bits of data.

Figure 9– 4 Four bits (1010) being entered serially into the register.

Figure 9– 5 Four bits (1010) being serially shifted out of the register and replaced by all zeros.

Shift Register – Logic Symbol • Logic symbol for an 8 -bit serial in/serial out shift register • SRG 8: a shift register (SRG) with an 8 -bit capacity

Serial In / Parallel Out Shift Register

Serial In / Parallel Out Shift Register EXAMPLE 9 -2 Show the states of the 4 -bit shift register (SRG 4) for the data input and clock waveform in Figure 9 -9(a). The register initially contains all 1 s.

Parallel In / Serial Out Shift Register

Parallel In / Serial Out Shift Register

Parallel In / Serial Out Shift Register EXAMPLE 9 -3 Show the data-output waveform for a 4 -bit register with the parallel input data and the clock and SHIFT/LOAD waveforms given in Figure 9 -13(a).

Parallel In / Parallel Out Shift Register

Bi-directional Shift Register In a bi-directional shift register, the data can be shifted either or right.

8. 8 Impediments to Synchronous Design

8. 8. 1 Clock Skew

Clock Skew • Synchronous systems using edge-triggered flip-flops work properly only if all flip-flops see the triggering clock edge at the same time. • The difference between arrival times of the clock at different devices is called clock skew. 63

Clock Skew 64

Clock Skew 65