Digital CMOS Logic Circuits 1 Figure 10 1
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Digital CMOS Logic Circuits 1
Figure 10. 1 Digital IC technologies and logic-circuit families. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 2
Figure 10. 2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 3
Figure 10. 3 Definitions of propagation delays and switching times of the logic inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 4
Figure 10. 4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 5
Figure 10. 5 The voltage transfer characteristic (VTC) of the CMOS inverter when QN and QP are matched. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 6
Figure 10. 6 Circuit for analyzing the propagation delay of the inverter formed by Q 1 and Q 2, which is driving an identical inverter formed by Q 3 and Q 4. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 7
Figure 10. 7 Equivalent circuits for determining the propagation delays (a) t. PHL and (b) t. PLH of the inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 8
Figure 10. 8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 9
Figure 10. 9 Examples of pull-down networks. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 10
Figure 10. 10 Examples of pull-up networks. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 11
Figure 10. 11 Usual and alternative circuit symbols for MOSFETs. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 12
Figure 10. 12 A two-input CMOS NOR gate. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 13
Figure 10. 13 A two-input CMOS NAND gate. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 14
Figure 10. 14 CMOS realization of a complex gate. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 15
Figure 10. 15 Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (10. 25). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (10. 26). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 10. 27). Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 16
Figure 10. 16 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 17
Figure 10. 17 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 18
Figure 10. 18 Circuit for Example 10. 2. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 19
Figure 10. 19 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load NMOS inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 20
Figure 10. 20 Graphical construction to determine the VTC of the inverter in Fig. 10. 19. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 21
Figure 10. 21 VTC for the pseudo-NMOS inverter. This curve is plotted for VDD = 5 V, Vtn = –Vtp = 1 V, and r = 9. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 22
Figure 10. 22 NOR and NAND gates of the pseudo-NMOS type. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 23
Figure 10. 23 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C). Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 24
Figure 10. 24 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 25
Figure 10. 25 A basic design requirement of PTL circuits is that every node have, at all times, a low-resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S 1 is open. It is provided in (b) through switch S 2. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 26
Figure 10. 26 Operation of the NMOS transistor as a switch in the implementation of PTL circuits. This analysis is for the case with the switch closed (v. C is high) and the input going high (v. I = VDD). Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 27
Figure 10. 27 Operation of the NMOS switch as the input goes low (v. I = 0 V). Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles comparison to the circuit in Fig. 10. 26. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 28
Figure 10. 28 The use of transistor QR, connected in a feedback loop around the CMOS inverter, to restore the VOH level, produced by Q 1, to VDD. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 29
Figure 10. 29 Operation of the transmission gate as a switch in PTL circuits with (a) v. I high and (b) v. I low. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 30
Figure 10. 30 Realization of a two-to-one multiplexer using pass-transistor logic. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 31
Figure 10. 31 Realization of the XOR function using pass-transistor logic. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 32
Figure 10. 32 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic or CPL. Note that both the output function and its complement are generated. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 33
Figure 10. 33 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 34
Figure 10. 34 (a) Charge sharing. (b) Adding a permanently turned-on transistor QL solves the charge-sharing problem at the expense of static power dissipation. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 35
Figure 10. 35 Two single-input dynamic logic gates connected in cascade. With the input A high, during the evaluation phase CL 2 will partially discharge and the output at Y 2 will fall lower than VDD, which can cause logic malfunction. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 36
Figure E 10. 12 Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 37
Figure 10. 36 The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, Y either will remain low (at 0 V) or will make one 0 -to-1 transition (to VDD). Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 38
Figure 10. 37 (a) Two single-input domino CMOS logic gates connected in cascade. (b) Waveforms during the evaluation phase. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 39
Figure 10. 38 Capture schematic of the CMOS inverter in Example 10. 5. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 40
Figure 10. 39 Input–output voltage transfer characteristic (VTC) of the CMOS inverter in Example 10. 5 with mp/mn = 1 and mp/mn = 4. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 41
Figure 10. 40 (a) Output voltage, and (b) supply current versus input voltage for the CMOS inverter in Example 10. 5 with mp/mn = 1 and mp/mn = 4. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 42
Figure 10. 41 Transient response of the CMOS inverter in Example 10. 5 with mp/mn = 1 and mp/mn = 4. Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 43
Figure P 10. 14 Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 44
Figure P 10. 36 Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 45
Figure P 10. 38 Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 46
Figure P 10. 49 Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 47
Figure P 10. 51 Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc. 48
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