Diagnostic Tests for PreBond TSV Defects Bei Zhang

Diagnostic Tests for Pre-Bond TSV Defects Bei Zhang Vishwani Agrawal VLSI Design & Embedded Systems Conference January 2015 Bengaluru, India

Purpose of Pre-bond TSV Test ØDefects arise in TSV manufacturing. Pre-bond TSV test helps identify defective dies early in the process. ØPre-bond TSV test provides known good die (KGD) information for die-on-die or die-onwafer or wafer-on-wafer fabrication process. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 2

Outline • • • 3 D IC Structure and TSV Models Pre-bond TSV Probing technique Test Session Generation Experimental Results Conclusion 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 3

TSV-based 3 D IC Structure l 3 D face-to-back stacked IC: 4 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 4

RC Models of Defective TSVs After Wafer Thinning Resistance-defective TSV Capacitance-defective TSV B. Noia and K. Chakrabarty, Design-for-Test and Test Optimization Techniques for TSV-based 3 D Stacked ICs. Springer, 2014. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 5

Illustration of Pre-bond TSV Probing on the Substrate Side GSF: Gated scan flip-flop 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 6

Circuit Model of Pre-bond TSV Test 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 7

Circuit Model of Pre-bond TSV Test 1 1 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 8

Circuit Model of Pre-bond TSV Test 1 1 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 9

Circuit Model of Pre-bond TSV Test 1 1 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 10

Capacitor Charging Time Through Parallel TSVs Number of TSVs charging in parallel (q) 1 2 3 4 Capacitor charging time t(q) (μs) 0. 80 0. 53 0. 42 0. 38 S. K. Roy, S. Chatterjee, C. Giri, and H. Rahaman, “Faulty TSVs Identification and Recovery in 3 D Stacked ICs During Pre-bond Testing, ” Proc. International 3 D Systems Integration Conference, 2013, pp. 1– 6. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 11

Two Important Observations 1) Any faulty TSV within a parallel test will cause the test to fail but we cannot tell which TSV(s) is (are) faulty. 2) A good parallel test implies that all TSVs within the parallel test are fault-free. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 12

Terminology TSV network TSVs simultaneously contacted by probe. Test session (Si) TSVs grouped for parallel charging of capacitor. Maximum number m is the number of redundant TSVs within the of faulty TSVs in TSV network (m) Session size (q) q is the number of active TSVs within a session. Resolution (r) r is an upper bound on session size. Test time of a session (t(q)) Fault map (ρ) Charging time of Ccharge, related to session size. 10/7/2020 Fault map represents positions of defective TSVs within the TSV network. © VLSI Design & Embedded Systems Conference - 2015 13

Test Session Generation ØMotivation Compared to individual TSV test, large test time saving is possible if we test TSVs in parallel without losing the capability of identifying up to m faulty TSVs, while guaranteeing that the size of each test session does not exceed the resolution constraint r. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 14

Test Session Generation ØProblem Statement Given: Test times t(q) for different session sizes q (q∈[1, r]), and Maximum number (m) of faulty TSVs in a network of T TSVs. Determine: A set of test sessions of size less than r, such that up to m faulty TSVs are uniquely identified and the total test time is minimized. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 15

Test Session Generation ØSufficient condition If each TSVi is included in m + 1 sessions (say, S 1, S 2, · · · , Sm+1) and the intersection of a pair of these m + 1 sessions contains only TSVi, i. e. , Si ∩ Sj = TSVi for i ≠ j ∈ [1, m + 1], then up to m faulty TSVs within the network can be uniquely identified. These m + 1 sessions are called unique test sessions for TSVi. B. Noia and K. Chakrabarty, “Identification of Defective TSVs in Pre-Bond Testing of 3 D ICs, ” Proc. 20 th Asian Test Symposium (ATS), 2011, pp. 187– 194. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 16

A Previous Heuristic Method To pinpoint 1 faulty TSV in a 6 -TSV network with resolution constraint r = 4, the heuristic-based sessions are {1, 2, 3, 4}, {1, 5, 6}, {2, 5}, {3, 6}, {4}. Careful examination shows: • Each TSV resides in two unique test sessions! • The heuristic sessions reduce the total test time compared to individual TSV testing. B. Noia and K. Chakrabarty, “Identification of Defective TSVs in Pre-Bond Testing of 3 D ICs, ” Proc. 20 th Asian Test Symposium (ATS), 2011, pp. 187– 194. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 17

Limitation of the Heuristic Method Ø Sessions {1, 2, 3, 4}, {1, 5, 6}, {2, 5}, {3, 6}, {4} are not optimal. The optimal set of sessions are {1, 2, 3}, {1, 4, 5}, {2, 4, 6}, {3, 5, 6} Ø As we can see every TSV still resides in 2 unique sessions, but the total test time is further reduced by 36. 8%! 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 18

ILP based Session Generation ØThree general constraints for ILP model (ILP model 1): C 1. Each TSV should be included in at least m + 1 test sessions. C 2. The size of a test session ranges anywhere from 0 (empty session) to r. C 3. Any non-empty session is supposed to be a unique session for any TSV within it. ØObjective: Minimize total test time of all sessions. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 19

Experimental Results Test time comparison for a 20 -TSV network 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 20

Experimental Results Test time comparison for resolution constraint r = 3 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 21

Experimental Results Comparison of number of sessions for r = 4 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 22

Conclusion • An ILP model is proposed to generate nearoptimal set of test sessions for pre-bond TSV testing. • ILP model always reduces pre-bond TSV identification time compared to that of a previous heuristic method. • Future exploration can be possibly deriving necessary and sufficient conditions to generate globally optimal set of sessions. 10/7/2020 © VLSI Design & Embedded Systems Conference - 2015 23