DET 218 3 ANALOGUE ELECTRONICS CHAPTER 2 Lecture

DET 218 / 3 ANALOGUE ELECTRONICS CHAPTER 2 Lecture I Introduction to Field Effect Transistors

FIELD EFFECT TRANSISTOR (FET) q. ADVANTAGES OF FET q. TYPES OF FET & ITS OPERATION

FET Advantages Why? Voltage-controlled amplifier input impedance very high Low noise output useful as preamplifiers when noise must be very low because of high gain in following stages Better linearity distortion minimized Low inter-electrode capacity at high frequency, inter-electrode capacitance can make amplifier work poorly. FET desirable in RF stages

Types of FET JFET MOSFET • n channel Enhancement mode • p channel • n channel • p channel Depletion mode • n channel • p channel MESFET

Junction FET (JFET) ohmic contact Structure n-channel p-channel Symbol

Metal-Oxide-Semiconductor FET (MOSFET) DEPLETION p n p dielectric ENHANCEMENT metal p n-channel p-channel

D-MOSFET SYMBOL

E-MOSFET SYMBOL

JFET Operation depletion region VDD VGG • Gate-source is reversed-biased • zero current at gate • IDS flow through the channel and determined by the width of depletion region and the width of the channel

MOSFET Operation electron inversion layer G S D SS • No voltage applied to gate • +ve voltage applied to gate • Current is zero • Electron inversion layer is created • Current is generated between source and drain

FET CHARACTERISTICS q JFET q MOSFET

JFET CHARACTERISTICS • DRAIN CHARACTERISTIC Constant current area VP=|VGS (off)|

JFET CHARACTERISTICS • TRANSFER CHARACTERISTIC

JFET DATA SHEET For MMBF 5459 VGS (off) = -8. 0 V (max) IDSS = 9. 0 m. A (typ. )

MOSFET CHARACTERISTICS • TRANSFER CHARACTERISTIC (Depletion MOSFET)

MOSFET CHARACTERISTICS • TRANSFER CHARACTERISTIC (Enhancement MOSFET) K in formula can be calculated by substituting data sheet values ID(on) for ID and VGS at which ID(on) is specified for VGS

E-MOSFET DATA SHEET ID(on) = 75 m. A (minimum) at VTN = 0. 8 V and VGS = 4. 5 V

FET BIASING q JFET BIAS CIRCUITS q. Self-bias q. Voltage-divider bias q MOSFET BIAS CIRCUITS q. Voltage-divider bias q. Drain-feedback bias

Equivalence biasing of JFET & BJT JFET BJT <==>

JFET Bias Circuits - Self-Bias +VDD RD IG = 0 RG RS

LOAD LINE - SELF-BIASED JFET Example Determine the Q-point for the JFET circuit. The transfer characteristic curve is given in the figure. +VDD 9 V RD 2. 2 K RG RS 10 M 680

For ID=0, VGS=-IDRS=(0)(680)=0 V From the curve, IDSS=4 m. A; so ID=IDSS=4 m. A ID (m. A) VGS=-IDRS=-(4 m)(680)=-2. 72 V 4 IDSS ID=2. 25 m. A VGS=-1. 5 V Q 2. 25 -VGS (V) -6 VGS(off) -2. 72 -1. 5

JFET Bias Circuits - Voltage-divider Bias +VDD RD R 1 ID VG R 2 RS

LOAD LINE - VOLTAGE-DIVIDER BIAS JFET Example Determine the Q-point for the JFET circuit. The transfer characteristic curve is given in the figure. +VDD 8 V R 1 RD 2. 2 M 680 R 2 2. 2 M RS 3. 3 K

For ID=0, A For VGS=0, B ID (m. A) 12 IDSS ID=1. 8 m. A VGS=-1. 8 V Q -VGS (V) -3 -1. 8 VGS(off) 1. 8 B 1. 2 A 4 VGS (V)

MOSFET Bias Circuits - Voltage-divider Bias +VDD R 1 R 2 RD

MOSFET Bias Circuits - Drain-Feedback Bias +VDD RG RD IG = 0

EXERCISES (Load Line JFET) 1. Determine the Q-point for the JFET circuit. The transfer characteristic curve is given in the figure. +VDD 6 V RD 820 ID (m. A) IDSS = 5 m. A -VGS (V) VGS(off)=-3. 5 RG RS 10 M 330

EXERCISES (Cont) 2. Determine the Q-point for the JFET circuit. The transfer characteristic curve is given in the figure. ID (m. A) IDSS = 5 m. A RD 3. 3 M 1. 8 K 2. 2 M VGS(off)=-4 V 12 V R 1 R 2 -VGS (V) +VDD RS 3. 3 K