Designing with Verilog EECS 150 Fall 2007 Lab

Designing with Verilog EECS 150 Fall 2007 – Lab Lecture #2 Shauki Elassaad Thanks to Young Lee, Greg Gibeling 3/4/2021 EECS 150 Lab Lecture #2 1

Today n n n n n 3/4/2021 Hierarchical Design Methodology Top-Down and Bottom-Up Partitioning & Interfaces Behavioral vs. Structural Verilog Administrative Info Blocking and Non-Blocking Verilog and Hardware Lab #2 Primitives EECS 150 Lab Lecture #2 2

Hierarchical Design Methodology n n Divide and conquer approach More efficient interms of design productivity. Hierarchy helps in management of large designs. Hierarchy allows for design collaboration. n n 3/4/2021 Design is broken to different modules. Each designer is responsible of a set of modules EECS 150 Lab Lecture #2 3

Top-Down vs. Bottom-Up (1) n Top-Down Design n n 3/4/2021 Think of the top-level picture of the project Identify main components/modules Think of inter-module communication Do not get bugged down with details EECS 150 Lab Lecture #2 4

Top-Down vs. Bottom-Up (2) n Top-Down Design n 3/4/2021 Ends here: EECS 150 Lab Lecture #2 5

Top-Down vs. Bottom-Up (3) n Bottom-Up Testing n n n 3/4/2021 Faster, Easier and Cheaper Test each little component thoroughly Allows you to easily replicate working components EECS 150 Lab Lecture #2 6

Partitioning & Interfaces (1) n Partitioning n n Break design into independent modules Decide what modules make sense n n n Each module should be: n n n 3/4/2021 This is crucial for successful implementation and management of your design. Think of functional components when deciding on module boundaries. A reasonable size Independently testable Successful partitioning allows easier collaboration on a large project EECS 150 Lab Lecture #2 7

Partitioning & Interfaces (2) n Interfaces n n How different partitions talk to one another A concise definition of signals and timing n n Must be clean n Don’t send useless signals across Bad partitioning might hinder this An interface is a contract n 3/4/2021 Timing is vital, do NOT omit it Lets other people use/reuse your module EECS 150 Lab Lecture #2 8

Behavioral vs Structural (1) n Behavioral description describes functionality of design. It is independent of implementation. n n Structural description defines and decides on an implementation of a module. n 3/4/2021 There is a one-to-many mapping between a behavioral module and a structural module. Here we map the design to actual cells/gates. EECS 150 Lab Lecture #2 9

Behavioral vs. Structural (2) n Rule of thumb: n n Behavioral doesn’t have sub-components Structural has sub-components: n n Most modules are mixed n 3/4/2021 Instantiated Modules Instantiated Gates Instantiated Primitives Obviously this is the most flexible EECS 150 Lab Lecture #2 10

Behavioral vs. Structural (2) 3/4/2021 EECS 150 Lab Lecture #2 11

Behavioral vs. Structural (3) 3/4/2021 EECS 150 Lab Lecture #2 12

Administrative Info n Lab Grading n n 3/4/2021 Get it in by the opening of the next lab Partial credit will be given for incomplete labs Card Key Access for All is coming soon! Start looking for partners! EECS 150 Lab Lecture #2 13

Blocking vs. Non-Blocking (1) Verilog Fragment Result always @ (a) begin b = a; c = b; end always @ (posedge Clock) begin b <= a; c <= b; end C=B=A A-----B-------C B = Old A C = Old B B A D Q Clock 3/4/2021 EECS 150 Lab Lecture #2 14

Blocking vs. Non-Blocking (2) n Use Non-Blocking for Flip. Flop Inference n n 3/4/2021 posedge/negedge require Non-Blocking Else simulation and synthesis wont match EECS 150 Lab Lecture #2 15

Blocking vs. Non-Blocking (3) n If you use blocking for Flip. Flops: YOU WILL NOT GET WHAT YOU WANT! always @ (posedge b = a; // b c = b; // c end // b isn’t needed Clock) begin will go away will be a Flip. Flop at all always @ (posedge Clock) begin c = b; // c will be a Flip. Flop b = a; // b will be a Flip. Flop end 3/4/2021 EECS 150 Lab Lecture #2 16

Blocking vs. Non-Blocking (4) Race Conditions file xyz. v: file abc. v: module XYZ(A, B, Clock); module ABC(B, C, Clock); input B, Clock; input C, Clock; output A; output B; reg A; reg B; always @ (posedge Clock) A = B; B = C; endmodule THIS IS WRONG 3/4/2021 EECS 150 Lab Lecture #2 17

Blocking vs. Non-Blocking (5) Race Conditions file xyz. v: file abc. v: module XYZ(A, B, Clock); module ABC(B, C, Clock); input B, Clock; input C, Clock; output A; output B; reg A; reg B; always @ (posedge Clock) A <= B; B <= C; endmodule THIS IS CORRECT 3/4/2021 EECS 150 Lab Lecture #2 18

Verilog and Hardware (1) assign Sum = A + B; reg [1: 0] Sum; always @ (A or B) begin Sum = A + B; end 3/4/2021 EECS 150 Lab Lecture #2 19

Verilog and Hardware (2) assign Out = Select ? A : B; reg [1: 0] Out; always @ (Select or A or B) begin if (Select) Out = A; else Out = B; end 3/4/2021 EECS 150 Lab Lecture #2 20

Verilog and Hardware (3) assign Out = Sub ? (A-B) : (A+B); reg [1: 0] Out; always @ (Sub or A or B) begin if (Sub) Out = A - B; else Out = A + B; end 3/4/2021 EECS 150 Lab Lecture #2 21

Verilog and Hardware (4) reg [1: 0] Out; always @ (posedge Clock) begin if (Reset) Out <= 2’b 00; else Out <= In; end 3/4/2021 EECS 150 Lab Lecture #2 22

Lab #2 (1) n Lab 2 Top n Accumulator n n Peak Detector n n 3/4/2021 Stores sum of all inputs Written in behavioral verilog Same function as Lab 1 Circuit Stores largest of all inputs Written in structural verilog EECS 150 Lab Lecture #2 23

Lab #2 (2) 3/4/2021 EECS 150 Lab Lecture #2 24

Lab #2 (3) Accumulator. v 3/4/2021 EECS 150 Lab Lecture #2 25

Lab #2 (4) Peak. Detector. v 3/4/2021 EECS 150 Lab Lecture #2 26

Primitives (1) 3/4/2021 wire SIntermediate, SFinal, CPropagrate, CGenerate; xor and or xor 1( and 1( xor 2( and 2( or 1( SIntermediate, CGenerate, SFinal, CPropagate, COut, In, SIntermediate, In, CGenerate, FDCE FF( . Q(. CE(. CLR(. D( Out), Clock), Enable), Reset), SFinal)); EECS 150 Lab Lecture #2 Out); CIn); CPropagate); 27

Primitives (2) 3/4/2021 wire SIntermediate, SFinal, CPropagrate, CGenerate; xor and or xor 1( and 1( xor 2( and 2( or 1( SIntermediate, CGenerate, SFinal, CPropagate, COut, In, SIntermediate, In, CGenerate, FDCE FF( . Q(. CE(. CLR(. D( Out), Clock), Enable), Reset), SFinal)); EECS 150 Lab Lecture #2 Out); CIn); CPropagate); 28

Primitives (3) 3/4/2021 wire SIntermediate, SFinal, CPropagrate, CGenerate; xor and or xor 1( and 1( xor 2( and 2( or 1( SIntermediate, CGenerate, SFinal, CPropagate, COut, In, SIntermediate, In, CGenerate, FDCE FF( . Q(. CE(. CLR(. D( Out), Clock), Enable), Reset), SFinal)); EECS 150 Lab Lecture #2 Out); CIn); CPropagate); 29