Designing Sequential Logic Circuits Jan M Rabaey Anantha
Designing Sequential Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic © Digital Integrated Circuits 2 nd Sequential Circuits
Sequential Logic Inputs Combinational Logic Current State Clock © Digital Integrated Circuits 2 nd Outputs Next State 2 storage mechanisms: • positive feedback • charge-based Sequential Circuits
Naming Conventions q In the text: § a latch is level sensitive § a register is edge-triggered q Many different naming conventions: § flip-flops (level or edge? ) § Transparency? § Dual edge/level © Digital Integrated Circuits 2 nd Sequential Circuits
Latch versus Register q Latch- stores if clock is low transparent if clock is high q Register- stores if clock rises, never transparent (mostly) D Q Clk Clk D D Q Q © Digital Integrated Circuits 2 nd Sequential Circuits
Latch-Based Design • N latch is transparent when f = 0 • P latch is transparent when f = 1 f N Latch Logic P Latch Logic © Digital Integrated Circuits 2 nd Sequential Circuits
Timing Definitions CLK t tsetup D thold DATA STABLE t Register D Q CLK tc lk 2 q Q © Digital Integrated Circuits 2 nd DATA STABLE t Sequential Circuits
Maximum Clock Frequency Register f Timing Constraints: tclk 2 q + tp(comb) + tsetup = T tcdreg + tcdlogic > thold First Constraint ensures clock is slow enough that Registers sample correct value LOGIC t. P(comb) © Digital Integrated Circuits 2 nd Second Constraint ensures that there is no path after the clock changes to alter the previously stored data Sequential Circuits
Positive Feedback: Bi-Stability Vi 2 V o 1 1 o V 52 i V V i 1 V o 2 A, B Stable points C is unstable: (metastable) Feedback moves state to Stable points, eventually A 1 o V 52 i V V i 2 = V o 1 C B V i 1 = V o 2 © Digital Integrated Circuits 2 nd Sequential Circuits
Writing a Static Latch Use the clock to distinguish between the transparent and opaque states CLK D D CLK Converting into a MUX © Digital Integrated Circuits 2 nd Forcing the state (can implement as NMOS-only) Sequential Circuits
Mux-Based Latches Negative latch (transparent when CLK= 0) 1 D 0 CLK © Digital Integrated Circuits 2 nd Positive latch (transparent when CLK= 1) 0 Q D Q 1 CLK Sequential Circuits
Master-Slave Register CLK D Qm Q CLK Two opposite latches trigger on edge Also called master-slave latch pair © Digital Integrated Circuits 2 nd Sequential Circuits
Clk-Q Delay D Tclk-q Clock to Q delays are Different for rising and falling Transitions Use Worst Case – not Avg! CLK Q © Digital Integrated Circuits 2 nd Sequential Circuits
Setup Time (MS register) Q Qm D Qm CLK Setup = 0. 21 n. S Passed D © Digital Integrated Circuits 2 nd Setup = 0. 20 n. S Failed to pass D Sequential Circuits
Cross-Coupled Pairs NOR-based set-reset © Digital Integrated Circuits 2 nd S Q R Q’ S 0 1 R 0 0 1 1 Q Q 1 0 - Q’ Q’ 0 1 - Sequential Circuits
Cross-Coupled NAND Cross-coupled NANDs Added clock This is not used in datapaths any more, but is a basic register memory cell © Digital Integrated Circuits 2 nd Sequential Circuits
Sizing Issues 2 Q’ (V) W=0. 5 1 W=0. 7 W=0. 8 2. 5 3. 0 3. 5 0 1 W=1 2 W/L (M 5, M 6) M 2=6 Output voltage dependence on transistor width © Digital Integrated Circuits 2 nd Transient response Sequential Circuits
Storage Mechanisms Dynamic (charge-based) Static CLK D Q CLK © Digital Integrated Circuits 2 nd Sequential Circuits
Making a Dynamic Latch Pseudo. Static © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Hold-1 case 0 © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Hold-1 case 0 © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Hold-1 case 0 © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Hold-1 case 0 © Digital Integrated Circuits 2 nd Sequential Circuits
Setup/Hold Time Illustrations Hold-1 case 0 © Digital Integrated Circuits 2 nd Sequential Circuits
Other Latches/Registers: C 2 MOS “Keepers” can be added to make circuit pseudo-static © Digital Integrated Circuits 2 nd Sequential Circuits
Insensitive to Clock-Overlap 0 VDD VDD M 2 M 6 M 4 D 0 X M 8 Q X D 1 M 1 (a) (0 -0) overlap © Digital Integrated Circuits 2 nd M 5 M 3 Q 1 M 7 M 5 (b) (1 -1) overlap Sequential Circuits
Pipelining Reference © Digital Integrated Circuits 2 nd Pipelined Sequential Circuits
Other Latches/Registers: TSPC Positive latch (transparent when CLK= 1) © Digital Integrated Circuits 2 nd Negative latch (transparent when CLK= 0) Sequential Circuits
Pulse-Triggered Latches An Alternative Approach Ways to design an edge-triggered sequential cell: Master-Slave Latches Data Pulse-Triggered Latch L 1 L 2 D Q Clk Data Clk L D Q Clk © Digital Integrated Circuits 2 nd Sequential Circuits
Latch-Based Pipeline ~CLK F F © Digital Integrated Circuits 2 nd CLK G G Sequential Circuits
Non-Bistable Sequential Circuits─ Schmitt Trigger • VTC with hysteresis • Restores signal slopes © Digital Integrated Circuits 2 nd Sequential Circuits
Noise Suppression: Schmitt Trigger © Digital Integrated Circuits 2 nd Sequential Circuits
CMOS Schmitt Trigger Moves switching threshold of the first inverter © Digital Integrated Circuits 2 nd Sequential Circuits
Schmitt Trigger Simulated VTC 2. 5 2. 0 VM 1 1. 5 (V) 1. 0 X V 1. 5 (V) 1. 0 x V VM 2 0. 5 0. 0 k=1 k=2 0. 5 1. 0 1. 5 Vin (V) 2. 0 2. 5 Voltage-transfer characteristics with hysteresis. © Digital Integrated Circuits 2 nd k=3 k=4 0. 0 0. 5 1. 0 1. 5 Vin (V) 2. 0 2. 5 The effect of varying the ratio of the PMOS device M 4. The width is k* 0. 5 m m. Sequential Circuits
CMOS Schmitt Trigger (2) © Digital Integrated Circuits 2 nd Sequential Circuits
Multivibrator Circuits © Digital Integrated Circuits 2 nd Sequential Circuits
Transition-Triggered Monostable © Digital Integrated Circuits 2 nd Sequential Circuits
Monostable Trigger (RC-based) © Digital Integrated Circuits 2 nd Sequential Circuits
Astable Multivibrators (Oscillators) Ring Oscillator 0 1 2 N-1 simulated response of 5 -stage oscillator © Digital Integrated Circuits 2 nd Sequential Circuits
Relaxation Oscillator © Digital Integrated Circuits 2 nd Sequential Circuits
Voltage Controller Oscillator (VCO) © Digital Integrated Circuits 2 nd Sequential Circuits
Differential Delay Element and VCO V o 2 V o 1 in 1 v 1 in 2 v 3 v 4 V ctrl delay cell two stage VCO 3. 0 2. 5 V 1 V 2 V 3 V 4 2. 0 1. 5 1. 0 0. 5 0. 0 2 0. 5 1. 5 2. 5 3. 5 time (ns) simulated waveforms of 2 -stage VCO © Digital Integrated Circuits 2 nd Sequential Circuits
Homework 7 1. 2. A common way to characterize registers is to measure the timing aperture which is the total window in which transitions on data are not correctly output. This is done by making two clocks which are close, but not the same so that the relative phase drifts slowly with each cycle. Construct a pseudo-static master/slave flip-flop in SUE with the assumption that the input is driven by a unit inverter (2/1, min width nmos), the clock is driven by a 2 x inverter. Optimize your designs to minimize the timing aperture (setup+hold) and clock to Q assuming the output load is 2 min inverters. Simulate your designs in SPICE and turn in both the designs (annotated schematics and spice results – plz. don’t waste paper!) Do problem 1 again, with TSPC based flipflop. (High performance) © Digital Integrated Circuits 2 nd Sequential Circuits
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