Designing Combinational Logic Circuits Part 2 Alternative Logic

Designing Combinational Logic Circuits: Part 2 Alternative Logic Forms: Ratio Logic Pass-Transistor Dynamic Logic © EE 141 Digital Integrated Circuits 2 nd 1 Combinational Circu

Ratio Logic VDD Resistive Load VDD Depletion Load RL PDN VSS (a) resistive load PMOS Load VSS VT < 0 F In 1 In 2 In 3 VDD F In 1 In 2 In 3 PDN VSS (b) depletion load NMOS F In 1 In 2 In 3 PDN VSS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS © EE 141 Digital Integrated Circuits 2 nd 2 Combinational Circu

Ratio Logic VDD • N transistors + Load Resistive Load • VOH = VDD RL • VOL = F In 1 In 2 In 3 RPN + RL • Assymetrical response PDN • Static power consumption VSS © EE 141 Digital Integrated RPN Circuits 2 nd • tp. L = 0. 69 RLCL 3 Combinational Circu

Active Loads VDD Depletion Load VDD PMOS Load VT < 0 VSS F In 1 In 2 In 3 PDN VSS depletion load NMOS © EE 141 Digital Integrated Circuits 2 nd F In 1 In 2 In 3 PDN VSS pseudo-NMOS 4 Combinational Circu

Pseudo-NMOS © EE 141 Digital Integrated Circuits 2 nd 5 Combinational Circu

Pseudo-NMOS VTC 3. 0 2. 5 W/Lp = 4 Vout [V] 2. 0 1. 5 W/Lp = 2 1. 0 0. 5 W/Lp = 1 W/Lp = 0. 25 0. 0 0. 5 1. 0 1. 5 2. 0 2. 5 Vin [V] © EE 141 Digital Integrated Circuits 2 nd 6 Combinational Circu

Improved Loads VDD M 1 Enable M 2 M 1 >> M 2 F A B C D CL Adaptive Load © EE 141 Digital Integrated Circuits 2 nd 7 Combinational Circu

Even Better Noise Immunity VDD M 1 VDD M 2 Out A A B B Out PDN 1 PDN 2 VSS Differential Cascode Voltage Switch Logic (DCVSL) © EE 141 Digital Integrated Circuits 2 nd 8 Combinational Circu

DCVSL Example Out B B A XOR-NXOR gate © EE 141 Digital Integrated Circuits 2 nd 9 Combinational Circu

DCVSL Transient Response V olta ge [V] 2. 5 AB 1. 5 0. 5 AB A, B -0. 5 0 © EE 141 Digital Integrated Circuits 2 nd 0. 2 A, B 0. 4 0. 6 Time [ns] 0. 8 1. 0 10 Combinational Circu

Pass-Transistor Logic Inputs B Switch Out A Network Out B A • N transistors • No static consumption © EE 141 Digital Integrated Circuits 2 nd 11 Combinational Circu

Example: AND Gate © EE 141 Digital Integrated Circuits 2 nd 12 Combinational Circu

NMOS-Only Logic 3. 0 Voltage [V] In Out 2. 0 x 1. 0 0 0. 5 1 1. 5 2 Time [ns] © EE 141 Digital Integrated Circuits 2 nd 13 Combinational Circu

NMOS-only Switch C = 2. 5 V C = 2. 5 V A = 2. 5 V B B M 2 Mn CL M 1 VB does not pull up to 2. 5 V, but 2. 5 V - VTN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) © EE 141 Digital Integrated Circuits 2 nd 14 Combinational Circu

NMOS Only Logic: Level Restoring Transistor VDD Level Restorer VDD Mr B A Mn M 2 X Out M 1 • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem © EE 141 Digital Integrated Circuits 2 nd 15 Combinational Circu

Restorer Sizing Voltage [V] 3. 0 2. 0 • Upper limit on restorer size • Pass-transistor pull-down can have several transistors in stack W/Lr =1. 75/0. 25 W/L r =1. 50/0. 25 1. 0 W/L r =1. 25/0. 25 W/Lr =1. 0/0. 25 0. 0 0 100 © EE 141 Digital Integrated 200 300 Time [ps] Circuits 2 nd 400 500 16 Combinational Circu

Solution 2: Single Transistor Pass Gate with VT=0 VDD 0 V 2. 5 V VDD 0 V VDD Out 2. 5 V WATCH OUT FOR LEAKAGE CURRENTS © EE 141 Digital Integrated Circuits 2 nd 17 Combinational Circu

Complementary Pass Transistor Logic © EE 141 Digital Integrated Circuits 2 nd 18 Combinational Circu

Solution 3: Transmission Gate C C A A B B C C C = 2. 5 V A = 2. 5 V B CL C=0 V © EE 141 Digital Integrated Circuits 2 nd 19 Combinational Circu

Resistance of Transmission Gate © EE 141 Digital Integrated Circuits 2 nd 20 Combinational Circu

Pass-Transistor Based Multiplexer S S VDD GND In 1 © EE 141 Digital Integrated Circuits 2 nd In 2 21 Combinational Circu

Transmission Gate XOR B B M 2 A A F M 1 B M 3/M 4 B © EE 141 Digital Integrated Circuits 2 nd 22 Combinational Circu

Delay in Transmission Gate Networks 2. 5 V 1 In 2. 5 Vi Vi-1 C 0 2. 5 C 0 Vn-1 Vi+1 C 0 Vn C C 0 (a) Req In Req V 1 Req Vi C Vn-1 Vi+1 C C Req Vn C C (b) m Req Req Req In C CC C (c) © EE 141 Digital Integrated Circuits 2 nd 23 Combinational Circu

Delay Optimization © EE 141 Digital Integrated Circuits 2 nd 24 Combinational Circu

Transmission Gate Full Adder Similar delays for sum and carry © EE 141 Digital Integrated Circuits 2 nd 25 Combinational Circu

Dynamic Logic © EE 141 Digital Integrated Circuits 2 nd 26 Combinational Circu

Dynamic CMOS q In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. § fan-in of n requires 2 n (n N-type + n P-type) devices q Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. § requires on n + 2 (n+1 N-type + 1 P-type) transistors © EE 141 Digital Integrated Circuits 2 nd 27 Combinational Circu

Dynamic Gate Clk Mp off Mp on Out In 1 In 2 In 3 Clk CL PDN 1 Out ((AB)+C) A C B Me Clk off Me on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) © EE 141 Digital Integrated Circuits 2 nd 29 Combinational Circu

Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. q Inputs to the gate can make at most one transition during evaluation. q q Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL © EE 141 Digital Integrated Circuits 2 nd 30 Combinational Circu

Properties of Dynamic Gates q Logic function is implemented by the PDN only § number of transistors is N + 2 (versus 2 N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) q Non-ratioed - sizing of the devices does not affect the logic levels q Faster switching speeds q § reduced load capacitance due to lower input capacitance (Cin) § reduced load capacitance due to smaller output loading (Cout) § no Isc, so all the current provided by PDN goes into discharging CL © EE 141 Digital Integrated Circuits 2 nd 31 Combinational Circu

Properties of Dynamic Gates q Overall power dissipation usually higher than static CMOS § no static current path ever exists between VDD and GND (including Psc) § no glitching § higher transition probabilities § extra load on Clk q PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn § low noise margin (NML) q Needs a precharge/evaluate clock © EE 141 Digital Integrated Circuits 2 nd 32 Combinational Circu

Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Clk Evaluate VOut Me Precharge Leakage sources Dominant component is subthreshold current © EE 141 Digital Integrated Circuits 2 nd 33 Combinational Circu

Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me Same approach as level restorer for pass-transistor logic © EE 141 Digital Integrated Circuits 2 nd 34 Combinational Circu

Issues in Dynamic Design 2: Charge Sharing Clk Mp Out A CL B=0 Clk Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness CA Me © EE 141 Digital Integrated CB Circuits 2 nd 35 Combinational Circu

Charge Sharing Example Clk A A B B B Cc=15 f. F C C Ca=15 f. F Out CL=50 f. F !B Cb=15 f. F Cd=10 f. F Clk © EE 141 Digital Integrated Circuits 2 nd 36 Combinational Circu

Charge Sharing VDD Clk Mp Out CL A Ma X B=0 Clk Mb Me © EE 141 Digital Integrated Ca Cb Circuits 2 nd 37 Combinational Circu

Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) © EE 141 Digital Integrated Circuits 2 nd 38 Combinational Circu

Issues in Dynamic Design 3: Backgate Coupling Clk Mp A=0 Out 1 =1 CL 1 Out 2 =0 CL 2 In B=0 Clk Me Dynamic NAND © EE 141 Digital Integrated Circuits 2 nd Static NAND 39 Combinational Circu

Voltage Backgate Coupling Effect Out 1 Clk In Out 2 Time, ns © EE 141 Digital Integrated Circuits 2 nd 40 Combinational Circu

Issues in Dynamic Design 4: Clock Feedthrough Clk Mp A Out CL B Clk Me © EE 141 Digital Integrated Circuits 2 nd Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. 41 Combinational Circu

Clock Feedthrough Clock feedthrough Clk Out In 1 In 3 Voltage In 2 In 4 In & Clk Out Clk Time, ns Clock feedthrough © EE 141 Digital Integrated Circuits 2 nd 42 Combinational Circu

Other Effects q Capacitive coupling q Substrate coupling q Minority charge injection q Supply noise (ground bounce) © EE 141 Digital Integrated Circuits 2 nd 43 Combinational Circu

Cascading Dynamic Gates V Clk Mp Out 1 Me Clk Out 2 In In Clk Me Out 1 VTn V Out 2 t Only 0 1 transitions allowed at inputs! © EE 141 Digital Integrated Circuits 2 nd 44 Combinational Circu

Domino Logic Clk In 1 In 2 In 3 Clk © EE 141 Digital Integrated Mp 1 1 1 0 PDN Me Circuits 2 nd Out 1 Clk 0 0 0 1 In 4 In 5 Clk Mp Mkp Out 2 PDN Me 45 Combinational Circu

Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Like falling dominos! © EE 141 Digital Integrated Circuits 2 nd 46 Combinational Circu

Properties of Domino Logic Only non-inverting logic can be implemented q Very high speed q § static inverter can be skewed, only L-H transition § Input capacitance reduced – smaller logical effort © EE 141 Digital Integrated Circuits 2 nd 47 Combinational Circu

Designing with Domino Logic VDD VDD Clk Mp Clk Out 1 Mp Mr Out 2 In 1 In 2 In 3 PDN In 4 Can be eliminated! Clk Me Inputs = 0 during precharge © EE 141 Digital Integrated Circuits 2 nd 48 Combinational Circu

Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage © EE 141 Digital Integrated Circuits 2 nd 49 Combinational Circu

Differential (Dual Rail) Domino off Mp Mkp Clk Out = AB 1 on Mkp 0 Clk Mp 1 A !A 0 Out = AB !B B Clk Me Solves the problem of non-inverting logic © EE 141 Digital Integrated Circuits 2 nd 50 Combinational Circu

np-CMOS Clk In 1 In 2 In 3 Clk Mp 1 1 1 0 PDN Me Out 1 Clk Me In 4 In 5 PUN 0 0 0 1 Clk Mp Out 2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN © EE 141 Digital Integrated Circuits 2 nd 51 Combinational Circu

NORA Logic Clk In 1 In 2 In 3 Clk Mp 1 1 1 0 Out 1 PDN Clk Me In 4 In 5 PUN 0 0 0 1 Clk Me to other PDN’s Mp Out 2 (to PDN) to other PUN’s WARNING: Very sensitive to noise! © EE 141 Digital Integrated Circuits 2 nd 52 Combinational Circu

Homework 6 Design (in Sue) a CPL version of the 16 bit ripple adder using transistors from the AMI 0. 6 process. Simulate in Hspice and measure the worst case delay and average power/MHz. 2. Design (in Sue and simulate) a Domino version of the same ripple adder – measure the w. c. delay and average power/MHz. (How do these designs compare to Static CMOS? ) 1. © EE 141 Digital Integrated Circuits 2 nd 53 Combinational Circu