Designing a Single Cycle Datapath In this lecture

Designing a Single Cycle Datapath In this lecture, slides from lectures 3, 8 and 9 from the course Computer Architecture ECE 201 by Professor Mike Schulte are used with permission.

The Big Picture: Where are We Now? ° The Five Classic Components of a Computer Processor Input Control Datapath Memory Output ° Today’s Topic: Design a Single Cycle Processor

The Big Picture: The Performance Perspective ° Performance of a machine is determined by: CPI • Instruction count • Clock cycle time • Clock cycles per instruction Inst. Count Cycle Time ° Processor design (datapath and control) will determine: • Clock cycle time • Clock cycles per instruction ° Single cycle processor - one clock cycle per instruction • Advantages: Simple design, low CPI • Disadvantages: Long cycle time, which is limited by the slowest instruction.

How to Design a Processor: step-by-step 1. Analyze instruction set => datapath requirements • the meaning of each instruction is given by register transfers R[rd] <– R[rs] + R[rt]; • datapath must include storage element for ISA registers • datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Design datapath to meet the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Design the control logic

MIPS Instruction set

Review: The MIPS Instruction Formats ° All MIPS instructions are 32 bits long. The three instruction formats are: 31 • R-type • I-type • J-type 26 op 6 bits 31 21 rs 5 bits 26 op 6 bits 31 rt 5 bits 21 rs 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits 16 rt 5 bits 0 immediate 16 bits 26 op 6 bits ° The different fields are: • • • 16 0 target address 26 bits op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction

Translating MIPS Assembly into Machine Language ° Humans see instructions as words (assembly language), but the computer sees them as ones and zeros (machine language). ° An assembler translates from assembly language to machine language. ° For example, the MIPS instruction add $t 0, $s 1, $s 2 is translated as follows (see back of book): Assembly Comment add op = 0, shamt = 0, funct = 32 $t 0 rd = 8 $s 1 rs = 17 $s 2 rt = 18 000000 op 10001 10010 rs rt 01000 00000 rd shamt 100000 funct

MIPS Addressing Modes ° Addressing modes specify where the data used by an instruction is located. mode example action register direct add $s 1, $s 2, $s 3 $s 1 = $s 2 + $s 3 immediate addi $s 1, $s 2, 200 $s 1 = $s 2 + 200 base+index lw $s 1 = mem[200 + $s 2] PC-relative beq $s 1, $s 2, 200 $s 1, 200($s 2) if ($s 1 == $s 2) PC = PC+4+200*4 Pseudo-direct j 4000 PC = (PC[31: 28], 4000*4) ° Often, the type of addressing mode depends on the type of operation being performed (e. g. , branches all use PC relative) ° A summary of MIPS addressing modes is given on the back cover of the book.

MIPS Addressing Modes/Instruction Formats • All MIPS instructions are 32 bits wide - fixed length Register (direct) op rs rt add $s 1, $s 2, $s 3 rd register Immediate Base+index op rs rt immed register addi $s 1, $s 2, 200 Memory + lw $s 1, 200($s 2) PC-relative op rs PC rt immed Memory + beq $s 1, $s 2, 200

Step 1 a: The MIPS Subset for Today ° ADD and SUB 31 op 6 bits • addu rd, rs, rt • subu rd, rs, rt ° OR Immediate: • ori rt, rs, imm 16 ° LOAD and STORE • lw rt, rs, imm 16 • sw rt, rs, imm 16 ° BRANCH: • beq rs, rt, imm 16 26 31 21 rs 5 bits 16 rt 5 bits 26 21 16 op 6 bits 31 26 op 6 bits rs 5 bits 21 rs 5 bits rt 5 bits 16 rt 5 bits 21 16 31 26 op 6 bits rs 5 bits rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits 0 immediate 16 bits

Register Transfer Logic (RTL) ° RTL gives the meaning of the instructions ° All instructions start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm 16 = MEM[ PC ] inst Register Transfers addu R[rd] <– R[rs] + R[rt]; PC <– PC + 4 subu R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ori R[rt] <– R[rs] + zero_ext(imm 16); PC <– PC + 4 load R[rt] <– MEM[ R[rs] + sign_ext(imm 16)]; PC <– PC + 4 store MEM[ R[rs] + sign_ext(imm 16) ] <– R[rt]; PC <– PC + 4 beq if ( R[rs] == R[rt] ) then PC <– PC + 4 + sign_ext(imm 16)] || 00 else PC <– PC + 4

Step 1: Requirements of the Instruction Set ° Memory • instruction & data ° Registers (32 x 32) • read rs • read rt • write rt or rd ° PC ° Extender (sign extend or zero extend) ° Add and sub register or extended immediate ° Add 4 or shifted extended immediate to PC

Step 2: Components of the Datapath ° Adder Carry. In A 32 ° MUX B 32 OP 32 32 ALU B Sum Carry 32 Y 32 ° ALU A 32 Select MUX A Adder B 32 3 32 Result Combinational Logic: Does not use a clock

Storage Element: Register (Basic Building Blocks) ° Register • Similar to the D Flip Flop except - N-bit input and output Write Enable Data In N Data Out N - Write enable input • Write Enable: Clk - negated (0): Data Out will not change - asserted (1): Data Out will become Data In on the falling edge of the clock

Clocking Methodology - Negative Edge Triggered Clk Setup Hold . . . Don’t Care . . . ° All storage elements are clocked by the same clock edge ° Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew

Storage Element: Register File ° Register File consists of 32 registers: Write Enable RWRARB 5 5 5 • Two 32 -bit output busses: bus. A and bus. B bus. W 32 32 32 -bit • One 32 -bit input bus: bus. W 32 Registers bus. B Clk ° Register is selected by: 32 • RA (number) selects the register to put on bus. A (data) • RB (number) selects the register to put on bus. B (data) • RW (number) selects the register to be written via bus. W (data) when Write Enable is 1 ° Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: - RA or RB valid => bus. A or bus. B valid after “access time. ”

Register File - Read ° Built using D flip-flops

Register File - write

Storage Element: Idealized Memory ° Memory (idealized) • One input bus: Data In • One output bus: Data Out ° Memory word is selected by: Write Enable Address 32 Data In 32 Clk Data. Out 32 • Address selects the word to put on Data Out • Write Enable = 1: address selects the memory word to be written via the Data In bus ° Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, memory behaves as a combinational logic block: - Address valid => Data Out valid after “access time. ”

Step 3 ° Register Transfer Requirements –> Datapath Design • Instruction Fetch • Decode instructions and Read Operands • Execute Operation • Write back the result

3 a: Overview of the Instruction Fetch Unit ° The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: - Sequential Code: PC <- PC + 4 - Branch and Jump: PC <- “something else” Clk PC Next Address Logic Address Instruction Memory Instruction Word 32

3 b: Add & Subtract ° R[rd] <- R[rs] op R[rt] Example: addu rd, rs, rt • Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields • ALUctr and Reg. Wr: control logic after decoding the instruction 31 26 op 6 bits 21 rs 5 bits 16 11 rt 5 bits rd 5 bits Rd Rs Rt Reg. Wr 5 5 5 shamt 5 bits funct 6 bits ALUctr 3 bus. A 32 bus. B 32 ALU bus. W 32 Clk Rw Ra Rb 32 32 -bit Registers 6 Result 32 0

3 c: Logical Operations with Immediate ° R[rt] <- R[rs] op Zero. Ext[imm 16] 31 26 op 6 bits Example : ori rt, rs, imm 16 21 rs 5 bits rt 5 bits 31 Rd Reg. Dst 11 16 16 15 0 immediate 16 bits rd? immediate 16 bits 00000000 16 bits Rt Mux Reg. Wr 5 32 Clk Rw Ra Rb 32 32 -bit Registers 32 bus. B 32 Mux 16 bus. A Zero. Ext imm 16 ALUctr 3 ALU bus. W Rs 5 5 32 ALUSrc Result 32 0

3 d: Load Operations ° R[rt] <- Mem[R[rs] + Sign. Ext[imm 16]] 31 26 op rs 6 bits Rd Rt Reg. Dst Mux Reg. Wr 5 32 Clk 5 bits 16 bits rd ALUctr 3 bus. A W_Src 32 ALUSrc Data In 32 Clk Mux 32 Ext. Op 32 Mem. Wr Mux bus. B 32 Extender 16 0 immediate Rs 5 5 Rw Ra Rb 32 32 -bit Registers imm 16 rt 5 bits 11 16 ALU bus. W 21 Example: lw rt, rs, imm 16 Wr. En Adr Data Memory 32

3 e: Store Operations ° Mem[ R[rs] + Sign. Ext[imm 16] <- R[rt] ] Example: sw rt, rs, imm 16 31 26 21 op rs 6 bits Rd Reg. Dst 16 0 rt 5 bits immediate 5 bits Rt 16 bits ALUctr Mem. Wr W_Src Mux Reg. Wr 5 32 Clk 5 Rw Ra Rb 32 32 -bit Registers 32 32 Ext. Op 32 Data In 32 Clk ALUSrc Wr. En Adr Data Memory Mux bus. B 32 Mux 16 bus. A Extender imm 16 3 Rt ALU bus. W 5 Rs 32

3 f: The Branch Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 0 immediate 16 bits ° beq rs, rt, imm 16 • mem[PC] Fetch the instruction from memory • Equal <- R[rs] == R[rt] Calculate the branch condition • if (COND eq 0) Calculate the next instruction’s address - PC <- PC + 4 + ( Sign. Ext(imm 16) x 4 ) else - PC <- PC + 4

Datapath for Branch Operations rs, rt, imm 16 31 26 Datapath generates condition (equal) 21 op rs 6 bits 16 rt 5 bits 0 immediate 5 bits 16 bits Inst Address n. PC_sel 4 Adder Reg. Wr 5 bus. W PC Mux 00 32 Clk Adder PC Ext imm 16 Cond Clk 5 Rs 5 Rt Rw Ra Rb 32 32 -bit Registers bus. A 32 bus. B 32 Equal? ° beq

Putting it All Together: A Single Cycle Datapath n. PC_sel Reg. Dst 00 5 Rs 5 Rt imm 16 16 Extender Clk = 32 0 1 32 Data In 32 Ext. Op Clk ALUSrc 32 0 Mux bus. A Rw Ra Rb 32 32 -bit Registers bus. B 32 Clk Memto. Reg 3 Mux PC Mux Adder PC Ext imm 16 ALUctr Mem. Wr Equal ALU Adder 32 Imm 16 0 Reg. Wr 5 bus. W Rd Rd Rt 1 4 Rt Instruction<31: 0> <0: 15> Rs <11: 15> Adr <16: 20> <21: 25> Inst Memory Wr. En Adr Data Memory 1

Step 4: Given Datapath: RTL -> Control Instruction<31: 0> Rd <0: 15> Rs <11: 15> Rt <16: 20> Op Fun <21: 25> <0: 5> Adr <26: 31> Inst Memory Imm 16 Control n. PC_sel. Reg. Wr Reg. Dst Ext. Op ALUSrc ALUctr Mem. Wr Memto. Reg DATA PATH Equal

A Single Cycle Datapath ° We have everything except control signals (underlined) • Today’s lecture will look at how to generate the control signals 1 Mux 0 Reg. Wr 5 5 Rs 5 Rt Rt ALUctr bus. A 0 1 32 Ext. Op Clk Imm 16 Memto. Reg Mem. Wr 0 32 Data In 32 ALUSrc Rd Wr. En Adr Data Memory 32 Mux 16 Extender imm 16 32 Mux 32 Clk Rw Ra Rb 32 32 -bit Registers bus. B 32 ALU bus. W Zero Rs <0: 15> Clk <11: 15> Reg. Dst Rt <16: 20> Rd Instruction Fetch Unit <21: 25> n. PC_sel Instruction<31: 0> 1

Meaning of the Control Signals ° Ext. Op: “zero”, “sign” ° ALUsrc: immed 0 => reg. B; 1 => ° ALUctr: “add”, “sub”, Reg. Dst Rd Rt Reg. Wr 5 ° Reg. Dst: 0 => “rt”; 1 => “rd” ° Reg. Wr: write dest register “or”Equal ALUctr Mem. Wr 5 Rt 32 0 1 32 Data In 32 Ext. Op Clk ALUSrc 32 0 Mux 16 Extender imm 16 = Mux bus. A Rw Ra Rb 32 32 -bit Registers bus. B 32 Clk Memto. Reg 3 ALU 32 5 Rs write memory ° Memto. Reg: 0 => ALU; 1 => Mem 0 1 bus. W ° Mem. Wr: Wr. En Adr Data Memory 1

RTL: The Add Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits ° add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address

The Single Cycle Datapath during Add/Sub 31 26 21 op rs 16 rt 11 6 rd shamt ° R[rd] <- R[rs] op R[rt] Zero ALU 16 Extender imm 16 1 32 Ext. Op = x Rd Clk Imm 16 Memto. Reg = 0 Mem. Wr = 0 0 32 Data In 32 ALUSrc = 0 Rs Wr. En Adr Data Memory 32 Mux bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt <0: 15> 5 ALUctr = Add Rt <11: 15> 5 Rs Mux 32 Clk 1 Mux 0 Reg. Wr = 1 5 bus. W Rt Instruction Fetch Unit <16: 20> Reg. Dst = 1 Rd funct Instruction<31: 0> <21: 25> n. PC_sel= +4 0 1

Instruction Fetch Unit at the End of Add ° PC <- PC + 4 • This is the same for all instructions except Branch and Jump Inst Memory Adr n. PC_sel = +4 4 00 Adder imm 16 PC Mux Adder Clk Instruction<31: 0>

The Single Cycle Datapath during Load 31 26 21 op rs 16 0 rt immediate ° R[rt] <- Data Memory {R[rs] + Sign. Ext[imm 16]} bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt Zero 32 Ext. Op = 1 Imm 16 Memto. Reg = 1 Mem. Wr = 0 0 32 Data In 32 ALUSrc = 1 Rd Clk Mux ALU 16 Extender imm 16 1 Rs <0: 15> 5 ALUctr = Add Rt <11: 15> 5 Rs Mux 32 Clk 1 Mux 0 Reg. Wr = 1 5 bus. W Rt <16: 20> Reg. Dst = 0 Rd Instruction Fetch Unit <21: 25> n. PC_sel= +4 Instruction<31: 0> 1 Wr. En Adr Data Memory 32

The Single Cycle Datapath during Store 31 26 21 op rs 16 0 rt immediate ° Data Memory {R[rs] + Sign. Ext[imm 16]} <- R[rt] Zero ALU 16 Extender imm 16 1 Ext. Op = 1 Rd 32 Clk Imm 16 Memto. Reg = x Mem. Wr = 1 0 32 Data In 32 ALUSrc = 1 Rs Wr. En Adr Data Memory 32 Mux bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt <0: 15> 5 ALUctr = Add Rt <11: 15> 5 Rs Mux 32 Clk 1 Mux 0 Reg. Wr = 0 5 bus. W Rt <16: 20> Reg. Dst = x Rd Instruction Fetch Unit <21: 25> n. PC_sel= +4 Instruction<31: 0> 1

The Single Cycle Datapath during Branch 31 26 21 op rs 16 0 rt immediate ° if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 5 Zero ALU 16 Extender imm 16 1 32 Ext. Op = x Rd Clk Imm 16 Memto. Reg = x Mem. Wr = 0 0 32 Data In 32 ALUSrc = 0 Rs Wr. En Adr Data Memory 32 Mux bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt <0: 15> 5 ALUctr = Subtract Rt <11: 15> 5 Rs Mux 32 Clk 1 Mux 0 Reg. Wr = 0 bus. W Rt <16: 20> Reg. Dst = x Rd Instruction Fetch Unit <21: 25> n. PC_sel= “Br” Instruction<31: 0> 1

Instruction Fetch Unit at the End of Branch 31 26 21 op rs 16 rt 0 immediate ° if (Zero == 1) then PC = PC + 4 + Sign. Ext[imm 16]*4 ; Inst Memory else PC = PC + 4 Instruction<31: 0> Adr n. PC_sel See book for what the datapath and control looks like for jump instructions. 4 00 Adder imm 16 PC Mux Adder Clk Compared to book our processor also supports the ORI instructions.

A Summary of the Control Signals See Appendix A func 10 0000 10 0010 We Don’t Care : -) op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 Reg. Dst ALUSrc Memto. Reg. Write Mem. Write n. PCsel Jump Ext. Op ALUctr<2: 0> 31 add 1 sub 1 ori 0 lw 0 sw x beq x jump x 0 0 1 0 0 0 x 1 0 0 0 0 1 1 1 0 0 0 1 1 x 0 1 0 x 0 0 1 0 x x x 0 0 0 1 x Add Subtract Or Add Subtract xxx 26 21 16 R-type op rs rt I-type op rs rt J-type op 11 rd 6 shamt immediate target address 0 funct add, sub ori, lw, sw, beq jump

Step 5: The Concept of Local Decoding op Reg. Dst ALUSrc Memto. Reg. Write Mem. Write Branch Jump Ext. Op ALUop<N: 0> op 6 00 0000 R-type 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 1 0 0 0 0 1 1 1 0 0 0 x 1 x 0 1 0 0 x 0 0 1 0 x x x 0 0 0 1 x “R-type” 0 Or 1 Add x x xxx Main Control ALU Control (Local) ALUctr 3 ALU func 6 ALUop N Subtract

The Encoding of ALUop op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 ° In this exercise, ALUop has to be N=2 bits wide to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: - (2) Or, (3) Add, and (4) Subtract ° To implement the full MIPS ISA, ALUop has to be 3 bits to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: - (2) Or, (3) Add, (4) Subtract (5) And (6) Set on < ALUop (Symbolic) ALUop<2: 0> R-type “R-type” 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 beq jump Subtract xxx 0 01

The Decoding of the “func” Field op Main Control 6 ALUop (Symbolic) ALUop<2: 0> 31 R-type func 6 ALUop N R-type “R-type” 1 00 26 op Get func from back of book for R-type funct<5: 0> 10 0000 10 0010 ori Or 0 10 21 rs Instruction Operation add subtract ALU Control (Local) lw Add 0 00 16 rt ALUctr 3 sw Add 0 00 11 rd beq jump Subtract xxx 0 01 6 shamt 0 funct Our processor only implements subset of operations ALUctr<2: 0> 000 ALU Operation Add Subtract And Or 10 0100 10 0101 and or 001 010 10 1010 set-on-less-than 111 Set-on-less-than

The Truth Table for ALUctr<2> R-type ALUop (Symbolic) “R-type” ALUop<2: 0> 1 00 ALUop bit<2> bit<1> bit<0> 0 0 x 1 0 1 x x 1 1 x x x x ori lw sw Or 0 10 Add 0 00 beq Subtract 0 01 func bit<3> bit<2> bit<1> bit<0> x x x 0 0 0 0 1 1 0 0 1 0 funct<3: 0> 0000 0010 0100 Instruction Op. add subtract and 0101 1010 or set-on-less-than ALU Operation Add Subtract Or Add Subtract And Or Set on < ALUctr bit<2> bit<1> bit<0> 0 1 1 0 0 0 1 0 1 0 0 1 1 This control is for more R-type instructions than our processor, but fewer than the entire MIPS ISA.

The Logic Equation for ALUctr<2> ALUop bit<2> bit<1> bit<0> 0 x 1 1 1 x x func bit<3> bit<2> bit<1> bit<0> x x 0 1 0 0 1 1 ° ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & func<1> 0 0 ALUctr<2> 1 1 1

The Truth Table for ALUctr <1> ALUop bit<2> bit<1> bit<0> 0 0 x 1 0 1 x x 1 1 x x x x func bit<3> bit<2> bit<1> bit<0> x x x 0 0 0 0 1 1 0 0 1 0 ALU Operation Add Subtract Or Add Subtract And Or Set on < ALUctr bit<2> bit<1> bit<0> 0 1 1 0 0 0 1 0 1 0 0 1 1

The Logic Equation for ALUctr<1> ALUop bit<2> bit<1> bit<0> 0 0 1 1 1 x x x func bit<3> bit<2> bit<1> bit<0> ALUctr<1> x x 1 x 0 0 0 x 0 1 1 ° ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & func<2> x 0 0 0 1 1

The Truth Table for ALUctr<0> ALUop bit<2> bit<1> bit<0> 0 0 x 1 0 1 x x 1 1 x x x x func bit<3> bit<2> bit<1> bit<0> x x x 0 0 0 0 1 1 0 0 1 0 ALU Operation Add Subtract Or Add Subtract And Or Set on < ALUctr bit<2> bit<1> bit<0> 0 1 1 0 0 0 1 0 1 0 0 1 1

The Logic Equation for ALUctr<0> ALUop bit<2> bit<1> bit<0> 0 1 x 1 1 x x func bit<3> bit<2> bit<1> bit<0> ALUctr<0> x x 1 0 1 1 0 ° ALUctr<0> = !ALUop<2> & ALUop<1> + ALUop< 2> & func<0> + ALUop<2> & func<3> 1 1

The ALU Control Block func 6 ALUop 3 ALU Control (Local) ALUctr 3 ° ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & func<1> ° ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & func<2> ° ALUctr<0> = !ALUop<2> & ALUop<1> + ALUop< 2> & func<0> + ALUop<2> & func<3>

The “Truth Table” for the Main Control op 6 Main Control Reg. Dst ALUSrc : ALUop func 6 ALU Control (Local) ALUctr 3 3 op Reg. Dst ALUSrc Memto. Reg. Write Mem. Write Branch Jump Ext. Op ALUop (Symbolic) ALUop <2> ALUop <1> ALUop <0> 00 0000 R-type 1 0 0 0 x “R-type” 1 0 0 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1 0 0 0 0 0 1 1 x x Or Add Subtract xxx 0 0 0 x 0 1 0 0 x 1

The “Truth Table” for Reg. Write op 00 0000 R-type 1 Reg. Write 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 1 1 0 0 0 ° Reg. Write = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw) . . op<5> <0> R-type . . op<5> <0> ori . . op<5> <0> lw . . op<5> <0> sw <0> beq . . op<5> op<0> jump Reg. Write

PLA Implementation of the Main Control . . op<5> <0> R-type . . op<5> <0> ori . . op<5> <0> lw . . op<5> <0> sw <0> beq . . op<5> jump op<0> Reg. Write ALUSrc Reg. Dst Memto. Reg Mem. Write Branch Jump Ext. Op ALUop<2> ALUop<1> ALUop<0>

Putting it All Together: A Single Cycle Processor ALUop op 6 Instr<31: 26> Rs 5 Rt Rt ALUctr bus. A 0 1 32 Ext. Op Clk Imm 16 Memto. Reg Mem. Wr 0 32 Data In 32 ALUSrc Rd Wr. En Adr Data Memory 32 Mux 16 Extender imm 16 Instr<15: 0> 32 Mux 32 Clk Rw Ra Rb 32 32 -bit Registers bus. B 32 ALU bus. W Zero Rs <0: 15> Clk <11: 15> 5 Instruction Fetch Unit <16: 20> Rt ALUctr 3 Instruction<31: 0> n. PC_sel 1 Mux 0 Reg. Wr 5 func Instr<5: 0> 6 ALUSrc : ALU Control <21: 25> Reg. Dst Main Control Rd 3 1

An abstract view of the critical path - load instruction Ideal Instruction Memory Instruction Rd Rs 5 5 Instruction Address Imm 16 A PC 32 Clk Rt 5 Rw Ra Rb 32 32 -bit Registers 32 32 ALU Next Address Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32 -bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew B 32 Data Address Data In Ideal Data Memory Clk Worst case delay for load is much longer than needed for all other instructions, yet this sets the cycle time.

An Abstract View of the Implementation Control Ideal Instruction Memory Instruction Rd Rs 5 5 A PC 32 Clk Conditions Rt 5 Rw Ra Rb 32 32 -bit Registers 32 32 ALU Next Address Instruction Address Control Signals B 32 Datapath ° Logical vs. Physical Structure Data Address Data In Clk Ideal Data Memory Data Out

Summary ° 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Design datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Design the control logic ° MIPS makes it easier • • Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates ° Single cycle datapath => CPI=1, CCT => long ° Next time: implementing control