Design of sequential circuits The general form of

Design of sequential circuits

The general form of a sequential circuit 2

Mealy and Moore Models of Finite State Machines In the Mealy model, the output is a function of both the present state and the input. In the Moore model, the output is a function of only the present state. 3

Mealy and Moore Models of Finite State Machines • The two models of a sequential circuit are commonly referred to as a finite state machine (FSM). • The Mealy model of a sequential circuit is referred to as a Mealy FSM or Mealy machine. • The Moore model is referred to as a Moore FSM or Moore machine. • In a Mealy model, the output is the value that is presented immediately before the active edge of the clock. • In a Moore model, the outputs of the sequential circuit are synchronized with the clock, because they depend only on flip-flop outputs that are synchronized with the clock. 4

Basic Design Steps 1. State Diagram 2. State Table 3. State Assignment 4. Choice of Flip-Flops 5. Derive Next-State and Output Expressions 6. Circuit Design Analysis Design Steps 5

Basic Design Steps • Example: • Design a circuit which detects if two or more consecutive 1 s occur. 6

Mealy and Moore Models of Finite State Machines • In a Mealy model, the output is the value that is presented immediately before the active edge of the clock. • In a Moore model, the outputs of the sequential circuit are synchronized with the clock, because they depend only on flip-flop outputs that are synchronized with the clock. 7

Mealy FSM Design 1. State Diagram 8

Mealy FSM Design 2. State Table 9

Mealy FSM Design 3. State Assignment 10

Mealy FSM Design 4. Choice of Flip-Flops and Derivation of Next-State and Output Expressions D FF 11

Mealy FSM Design 5. Design of Circuit 12

Mealy and Moore Models of Finite State Machines • In a Mealy model, the output is the value that is presented immediately before the active edge of the clock. • In a Moore model, the outputs of the sequential circuit are synchronized with the clock, because they depend only on flip-flop outputs that are synchronized with the clock. 13

Moore FSM Design 1. State Diagram 14

Moore FSM Design 2. State Table 17

Moore FSM Design 3. State Assignment 18

Moore FSM Design 4. Choice of Flip-Flops and Derivation of Next-State and Output Expressions D FF 19

Moore FSM Design 5. Design of Circuit 20

Moore FSM Design Timing Diagram 21

Mealy and Moore Output Timing Diagram z. Moore=y ZMealy=wy A key difference between the Mealy and Moore types of FSMs is that in the former a change in inputs reflects itself immediately in the outputs, while in the latter the outputs do not change until the change in inputs forces the machine into a new state, which 22

Example: Swap two registers contents Problem: Design a circuit to allow the contents of two registers to be swapped. 23

Example: Serial Adder Problem: Design a circuit to add of two n-bit registers in serial fashion. 24

Example: Serial Adder Mealy FSM Design 25

Example: Serial Adder Mealy Design State Table 26

Example: Serial Adder Mealy Design State Table State Assigned Table 27

Example: Serial Adder Mealy Design State Assigned Table 28

Example: Serial Adder Moore FSM Design 29

Example: Serial Adder Moore Design State Table 30

Example: Serial Adder Moore Design State Table State Assigned Table 31

Example: Serial Adder Moore Design State Assigned Table 32

Example: Serial Adder Mealy Design Moore Design A key difference between the Mealy and Moore types of FSMs is that in the former a change in inputs reflects itself immediately in the outputs, while in the latter the outputs do not change until the change in inputs forces the machine into a new state, which takes place one clock cycle later. 33

Example: Swap two registers contents Problem: Design a circuit to allow the contents of two registers to be swapped. (n-bit) A control circuit is used to ensure that only one of the tristate buffer enable inputs, R 1 out, . . . , Rkout, is asserted at a given time. The control circuit also produces the signals R 1 in, . . . , Rkin, which control when data is loaded into each register. (n-bit) n-bit tri-state buffer A digital system with k registers. 34

Example: Swap two registers contents (n-bit) A digital system with k registers. 35

Example: Swap two registers contents Moore FSM Design Mealy FSM Design 36

Example: Swap two registers contents Moore Design State Table 37

Example: Swap two registers contents Moore Design State Table State Assigned Table 38

Example: Swap two registers contents Moore Design State Assigned Table Outputs Next states 39

Example: Swap two registers contents Moore Design 40

Homework: Swap two registers contents. Design by T and JK FFs Mealy FSM Design 41

Example: Vending Machine Suppose that a coin-operated vending machine dispenses candy under the following conditions: • The machine accepts nickels and dimes. • It takes 15 cents for a piece of candy to be released from the machine. • If 20 cents is deposited, the machine will not return the change, but it will credit the buyer with 5 cents and wait for the buyer to make a second purchase. 42