Design of Regular Quantum Circuits Regular circuit tilebased

Design of Regular Quantum Circuits Regular circuit = tile-based circuit

REVERSIBLE LOGIC 2

Reversible Permutative logic Gates and Circuits ü A logic gate is reversible if Each input is mapped to a unique output It permutes the set of input values ü A combinational logic circuit is reversible if it satisfies the following: Has only one Fanout, Uses only reversible gates, No feedback path, has as many input wires as output wires, and permutes the input values. 3

Basic Reversible Gates NOT gate Controlled-NOT or Feynman gate a 0 0 1 1 b 0 1 a c 0 0 0 1 1 0 4

Basic Reversible Gates Toffoli gate (Controlled-Controlled NOT gate) a b c a b f 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 5

Basic Reversible Gates Swap gate Implementation of Swap gate using controlled-NOT 6

Basic Reversible Gates Fredkin gate (Controlled SWAP gate) a b c a f g 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 7

ALGORITHMS FOR SYNTHESIS OF REVERSIBLE LOGIC CIRCUITS 8

Popular Algorithms for Synthesis of Reversible Logic Circuits ü MMD: Transformation based ü Gupta-Agrawal-Jha: PPRM based ü Mishchenko-Perkowski: Reversible wave cascade ü Kerntopf: Heuristics based ü Wille: BDD based synthesis 9

reed-mul. LER EXPANSION IN SYNTHESIS OF REVERSIBLE CIRCUITS 10

IDEA: use reed-mul. LER EXPANSION IN SYNTHESIS OF REVERSIBLE CIRCUITS A New Representation is Reed-Muller Expansion (Positive Polarity Reed-Muller). This idea appeared for the first time in paper of Aggrawal and Jha, this paper was a competitor to MMD algorithm. Now we design a new algorithm which takes into account multi-level expansion for reversible circuits. 11

Example of Agrawal-Jha Algorithm c b a co bo ao 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 PPRM form for each output in terms of Input variables are given as follows and node is created • Reversible function specification is given as a truth table shown here • Output c 0, b 0 and a 0 are derived using EXORCISM-2 developed at PSU and parent node is created 12

Agrawal-Jha Algorithm (cont. . ) ü Parent node is explored by examining each output variable in the PPRM expansion. ü Factors are searched in the PPRM expansions that do not contain the same input variable. ü For example in the expansion below appropriate terms are “c” and “ac” ü The substitution is performed as ü In this example OR 13

Agrawal-Jha Algorithm (cont. . ) 14

Agrawal-Jha Algorithm (cont. . ) New nodes are created based on substitution 15

Next stage of Aggrawal-Jha algorithm 16

Next stage of Aggrawal-Jha algorithm 17

Solution found by the Aggrawal-Jha algorithm 18

Problem with Current Synthesis Approaches ü Common problem with current approaches: they invariably use nxn Toffoli gates, that might imposes technological limitations. ü High Quantum cost of Toffoli gates with many inputs. ü Synthesize only reversible functions, not Boolean functions that is not reversible. 19

Quantum Cost of 4 x 4 Toffoli Gate Implementation of 4 x 4 Toffoli gate with Quantum realizable 2 x 2 primitives such as controlled-V, controlled-NOT, controlled-V+. 20

CREATING QUANTUM ARRAY FROM LATTICE 21

Expansions Rules for Lattice DIAGRAAMS ü Positive Davio Tree can be created by expanding PPRM function using positive Davio expansion. ü Positive Davio Lattice is created by performing joining operation for neighboring cells at every level. ü Other Lattices can be created using similar method but using expansions such as Shannon or Negative Davio expansions or combination of them. 22

Creating Quantum Array from Lattices ü On the previous foils I showed representation of the Davio and Shannon cells as cascade of reversible gates. ü Next I present unique method to create Quantum Array from Positive Davio Lattice. ü The same approach can be used for other Lattices. 23

Creating Positive Davio Lattice ² Each node represents p. Dv cell. 24

Creating Quantum Array from Positive Davio Lattice + + c 1 1 + d d 1 + + 1 1 b b + a + 1 a 1 + 1 1 0 1 a 1 1 d 1 25

Quantum Array Representation a b c d d 0 1 Å a garbage 1 1 Å ad garbage 1 1 Å ab Å b garbage 1 0 garbage a b Å abd Å a b Å a Å d Å bd garbage 1 Å db Å ad Å abd Å bc Å ac Å cd Å bcd 1 function 1 Å db Å abd Å ad 26

Quantum Array Representation a b c d d 0 1 Å a garbage 1 1 Å ad garbage 1 1 Å ab Å b garbage 1 0 garbage a b Å abd Å a b Å a Å d Å bd garbage 1 Å db Å ad Å abd Å bc Å ac Å cd Å bcd 1 function 1 Å db Å abd Å ad 27

Creating Positive Davio Lattice ² Each node represents p. Dv cell. 28

Quantum Array Representation 29

Advantages of Lattice to QA ü Reversible circuit synthesized with only 3 x 3 Toffoli gates. ü Generates reversible circuit for any ESOP. ü Adds ancilla bits but overall cost of the circuit will be lower due to use of low cost 3 x 3 Toffoli gates. 30

Calculating Single-Output Shannon Lattice for Completely Specified Boolean Function. 31

Calculating Multi. Output Shannon Lattice for Completely Specified Boolean Function. 32

Calculating Multi-Output Shannon Lattice for Completely Specified Boolean Function. 33

DIPAL GATES, DIPAL GATE FAMILIES AND THEIR ARRAYS 34

Representation of pdv cell as a toffoli gate 35

Development of Dipal gate a b c Dipal cell representation with reversible gates Shannon cell f =ab Åac a a b f =ab Åac c b Åc ² Dipal gate is a reversible equivalent of Shannon cell ² There are 23! = 8! = 40320 3 x 3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose. • Find the reversible counterpart of well-known structures BDD, Lattices, KFDD • Show Dipal cell is between Toffoli and Fredkin 36

Development of Dipal gate (cont. . ) Dipal cell with negative variable represented with reversible gates Shannon cell with negative variable a b c a a b b Åc c f =ac Åab 37

Development of Dipal gate a b c Dipal cell representation with reversible gates Shannon cell f =ab Åac a a b f =ab Åac c b Åc ² Dipal gate is a reversible equivalent of Shannon cell ² There are 23! = 8! = 40320 3 x 3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose. 38

Dipal gate truth table c b a a 0 0 0 0 1 1 0 1 1 1 0 1 2 6 1 0 0 3 5 1 0 1 1 4 4 1 1 0 0 1 0 5 7 1 1 1 0 1 1 6 2 7 3 inpu outpu t t 39

Dipal gate unitary matrix 000 001 010 011 100 101 110 111 40

Variants of Dipal gates This is called a Dipal Gate Family General view of Dipal Family Gate 41

EXPERIMENTAL RESULTS 42

Results with Pdv Lattice and comparison with MMD and AJ results Benchmark 2 to 5 #Real inputs 5 #Garbage #Gates inputs Lattice 4 31 Cost Lattice 107 CPU time Lattice 0. 12 #Gates DMM 15 Cost DMM 107 #Gates AJ 20 Cost AJ 100 rd 32 3 1 4 8 < 0. 01 4 8 rd 53 5 5 11 39 < 0. 01 16 75 13 116 3_17 3 1 10 21 < 0. 01 6 12 6 14 6 sym 10 6 34 150 0. 37 20 62 NA NA 5 mod 5 5 1 14 58 < 0. 01 10 90 11 91 4 mod 5 4 1 6 18 < 0. 01 5 13 ham 3 3 0 3 7 < 0. 01 5 7 5 9 xor 5 5 0 4 4 < 0. 01 4 4 Xnor 5 5 1 5 5 < 0. 01 ---------- decod 24 4 2 10 30 < 0. 01 ---------- 11 31 Cycle 10_2 12 6 180 860 27. 9 19 1198 ---------- ham 7 7 5 22 58 0. 10 23 81 24 68 43

Results with Pdv Lattice and comparison with MMD and AJ results (cont. . ) Benchmark graycode 6 #Real inputs 6 #Garbage inputs 5 #Gates Lattice 5 Cost Lattice 5 CPU time #Gates Lattice DMM < 0. 01 5 Cost DMM 5 #Gates AJ 5 Cost AJ graycode 10 10 9 9 9 < 0. 01 9 9 graycode 20 20 19 19 19 < 0. 01 19 19 nth_prime 3_ inc nth_prime 4_ inc nth_prime 5_ inc alu 3 4 4 6 < 0. 01 4 6 ---------- 4 5 16 48 < 0. 01 12 58 ---------- 5 5 29 91 0. 22 26 78 ---------- 5 2 5 17 < 0. 01 ---------- 18 114 4_49 4 4 16 52 0. 04 16 58 13 61 hwb 4 4 4 12 28 < 0. 01 17 63 15 35 hwb 5 5 5 24 96 1. 2 24 104 ---------- hwb 6 6 6 32 128 2. 0 42 140 ---------- pprm 1 4 4 9 33 < 0. 01 ---------- 5 44

Results with shannon Lattice Benchmark 2 to 5 #Inputs #Gates p. Dv Lattice 5 31 Cost p. Dv Lattice 107 #Gates Shannon Lattice 41 Cost Shannon Lattice 117 rd 32 3 4 8 rd 53 5 11 39 18 46 3_17 3 10 21 15 26 6 sym 10 34 150 51 167 5 mod 5 5 14 58 30 81 4 mod 5 4 6 18 12 24 Ham 3 3 3 7 6 10 xor 5 5 4 4 Xnor 5 5 5 Decod 24 4 10 30 20 40 Cycle 10_2 12 180 860 270 950 Ham 7 7 22 58 32 68 45

Results with shannon Lattice (cont. . ) Benchmark Graycode 6 #Inputs #Gates p. Dv Lattice 6 5 Cost p. Dv Lattice 5 #Gates Shannon Lattice 5 Cost Shannon Lattice 5 Graycode 10 10 9 9 Graycode 20 20 19 19 nth_prime 3_ inc nth_prime 4_ inc nth_prime 5_ inc Alu 3 4 6 6 8 4 16 48 29 61 5 29 91 39 101 5 5 17 10 22 4_49 4 16 52 22 58 Hwb 4 4 12 28 15 31 Hwb 5 5 24 96 38 110 Hwb 6 6 32 128 40 134 Pprm 1 4 9 33 14 38 46

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• Fig. 2. Circuit for function FX 2 created with our method for traditional cost function calculation that does not take Ion Trap technology constraints into account. 49

Nearest Linear Node Model All gates are realized only on neighbors, but we have to add many SWAP gates • Fig. 3. Circuit from Figure 2 modified with adding SWAP gates for new cost function calculation that does take Ion Trap technology constraints into account, with XX gates added. It has 36 SWAP gates 50 added to realize LNNM.

Example of Positive Davio Lattice from [Perkowski 97 d]. Positive Davio Expansion is applied in 51 each node. Variable d is repeated

Transformation of function F 3(a, b, c) from classical Positive Davio Lattice to a Quantum Array with Toffoli and SWAP gates. Each SWAP gate is next replaced with 3 Feynman gates. (a) intermediate form, (b) final Quantum Array. 52

Intermediate Structure with Dipal Gate 53

Another Representation of Quantum Array with Dipal Gate 54

Layered Diagram using Dipal Gate ² General layout of the layered diagram ² Each box represents a gate from family of Dipal gate 55

General Pattern of Circuit with Dipal Gate 56

Quantum cost based On 1 d model Benchmark #Gates Lattice Cost Lattice 2 to 5 31 107 #Gates with SWAP insertion for Lattice 61 rd 32 4 8 8 rd 53 11 39 3_17 10 6 sym Cost with SWAP gates for Lattice 197 #Gates DMM Cost DMM 15 107 #Gates with SWAP insertion for MMD 31 Cost with SWAP gates for MMD 155 20 4 8 6 14 44 138 16 75 72 273 21 14 33 6 12 8 18 34 150 56 216 20 62 78 236 5 mod 5 14 58 17 67 10 90 48 204 4 mod 5 6 18 10 30 5 13 11 31 Ham 3 3 7 5 7 7 13 Xor 5 4 4 4 4 Xnor 5 5 5 -------- decod 24 10 30 14 42 -------- Cycle 10_2 180 860 306 1238 19 1198 199 1738 Ham 7 22 58 30 112 23 81 79 249 57

Quantum cost based On 1 d model Benchmark #Gates Lattice Cost Lattice Graycode 6 5 5 #Gates with SWAP insertion for Lattice 5 Graycode 10 9 9 9 Graycode 20 19 19 Nth_prime 3 _inc Nth_prime 4 _inc Nth_prime 5 _inc Alu 4 Cost with SWAP gates for Lattice 5 #Gates DMM Cost DMM 5 5 #Gates with SWAP insertion for MMD 5 Cost with SWAP gates for MMD 5 9 9 9 19 19 19 6 5 9 4 6 6 12 16 48 20 60 12 58 18 76 29 91 39 121 26 78 128 384 5 17 7 23 ---------- 4_49 16 52 41 127 16 58 40 130 hwb 4 12 28 15 40 17 63 39 129 hwb 5 24 96 44 156 24 104 64 224 hwb 6 32 128 72 248 42 140 144 446 pprm 1 9 33 19 63 ---------- 58

GENERALIZED REGULARITIES FOR QUANTUM AND NANOTECHNOLOGIES 59

Ion-Trap Layout (a) (b) (c) Interaction between two ions Single ion (d) Various regular structures are technically possible, single dimensional vector is the one that is most often discussed 60

Examples of Expansions for regular structures 61

Non-symmetric functions require repeatition of input variables • Variable b is repeated 62

Symmetry Indices and regular structures for binary logic 63

EXAMPLE: MULTI-VALUED REVERSIBLE LOGIC ADDER 64

MULTI-VALUED REVERSIBLE LOGIC 65

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Three dimensional realization of lattices for ternary logic: SUM 68

Three dimensional realization of lattices for ternary logic: CARRY 69

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QUANTUM CIRCUITS AND QUANTUM ARRAYS FROM TRULY QUANTUM GATES 71

Binary Reversible Gates ü Basic single qubit quantum gates 72

• The transformations of blocks of quantum gates to the pulses level. 73

• • Transformation of the circuit realized in Fig. 7 using Toffoli gate. Each Toffoli and SWAP gates are replaced by quantum CNOT and CV/CV+ quantum gates and rearranged to satisfy the neighborhood requirements of Ion trap. 74

Lattice based FPGA in CLASSICAL LOGIC 75

New type of FPGA in CMOS In classical CMOS logic one can design a regular array, such as a form of FPGA, which realizes Shannon, positive Davio and negative Davio inside one cell. Such array is highly testable We can try to design something similar in quantum and reversible logic circuits. 76

Design of SRFPGA cell 1. Dipal completed his MS in December 2000 with thesis on “Method for Self. Repair of FPGAs”. 2. I adapted concept of Lattices which were developed Dr. Perkowski and Dr. Jeske to design FPGA like regular structure in VLSI This cell can be mapped to Shannon, positive Davio, negative Davio and other logic gates. 77

General idea of SRFPGA architecture • General idea of the SRFPGA architecture, each circle represents cell shown on the previous foil. • Row and column decoders are for memory addressing 78 • The next foil shows actual physical design of the SRFPGA

SRFPGA layout With I/O pins 79

1 Var 1 var 2 var 3 var 4 var 5 var 6 var 7 var 8 var 9 var 10 var 11 var 12 var 13 var 14 var 15 var 16 1 1 1 Faults observed during column test C = 2. Test output 1 1 1 1 0 1 I 1 n 1 p 1 u 1 t 1 e 1 s 1 t 1 v 1 e 1 c 1 t 1 o 1 r 1 0 1 1 1 1 1 Faults observed during diagonal test D=2 T e s t o u Total number of t Faults N = C * D p = 2 * 2 = 4. u t 1 1 1 1 Input test vector 1 1 80

1. Dipal developed a unique test that identifies any number of faulty cell in the FPGA 2. Repair is based on redundancy-repair where identified faulty cells are replaced with unused good cell in the structure 3. Later Dipal adapted concept of lattice and synthesis methodology for designing reversible logic circuits. 4. His method of reversible circuit design resolves many issues that are not yet addressed by any other researchers 5. This approach can be extended to reversible and quantum logic cicuits.

CONCLUSIONS and possible projects 82

Conclusions ü Experimental results proved that our algorithm produced better results in terms of quantum cost compared to other contemporary algorithms for synthesis of reversible logic. ü New gate family called Dipal gate ü Presented new synthesis method with layered diagrams. ü ü More accurate technology specific cost model for 1 D qubit neighborhood architecture. 83

CONCLUSIONS ü A new method based of lattice diagram to synthesize reversible logic circuit with 3 x 3 Toffoli gates. ü A new family of gates called Dipal Gates. ü New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic function. ü Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice to QA). ü Program to implement a variant of MMD algorithm. 84

Possible Projects 1. 2. 3. 4. Generalize to ternary logic Generalize to all Dipal Gate Family gates. Realization with low level pulses for NMR technology. Development of a concept of reversible/quantum FPGA similar to SRFPGA 5. Extend Agrawal-Jha method for factorized circuits. 6. Extend the methods to many-output circuits. 85

What to remember? 1. 2. 3. 4. 5. 6. 7. 8. Use of PPRM in synthesis of reversible circuits. The main idea of Agrawal-Jha algorithm. How AJ algorithm can be improved? How this algorithm can be extended to Fredkin gates? Expansions Rules for Lattice Diagrams Creating Positive Davio Lattice Creating Negative Davio Lattice Creating Lattice for arbitrary function with a mixture of Davio and Shannon Expansions. 9. Lattices for symmetric functions. 10. Transforming Positive Davio Lattice to a quantum array 86 (circuit) for single output functions.

What to remember? 1. Transforming Positive Davio Lattice to a quantum array (circuit) for single output functions. 2. Transforming Positive Davio Lattice to a quantum array (circuit) for multi-output functions. 3. Dipal gate and Dipal gate family. 4. Regular structures and their use in quantum computing. 5. Regularity versus LNNM model. 6. Multiple-valued Lattices for ternary logic. 7. FPGA based on 3*3 lattices and can they be adapted to quantum and reversible circuits. 8. Decomposition to pulses. Relation to quantum costs. 87