Design of an 8 Bit Barrel Shifter Gene

Design of an 8 Bit Barrel Shifter Gene Vea, Perry Hung, Ricardo Rosas, Kevin Yoo Advisor: D. Parent May 11, 2005 1

Agenda • Abstract • Introduction – Why – Simple Theory – Back Ground information (Lit Review) • • • Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions 2

Abstract • Summarize the logic, clock frequency, area, and power specs of your final design • We designed an 8 -bit barrel shifter that operated at 200 MHz • 20 m. W of Power • Area of 370 x 350 mm 2 3

Introduction • The barrel shifter is a very important part of a combinational logic block. It was incorporated the 386 processor and is also used in microcontrollers. Intel has since moved on to software implemented barrel shifters in their Pentium 4’s but AMD still uses it to this day. • The designed circuit should shift a data word by any number of bits in a single operation. An N-bit shifter would require log 2 N number of levels to implement. For an 8 bit barrel shifter, it would require 3 logic levels. 4

Project Summary • Project was implemented with an array of 24 MUXs and 19 DFF MUXs arranged in three stages. • Implemented with the new DFF MUXs designed in class 5

Project Details • Explain all the details of your project. – Schematics should be legible, and not too busy. – If you did a set of experiments describe the conditions you did them under. – show a table with all hand calculations for your longest path • Show – Final schematic (not test bench) – Final layout – Final simulation 6

Longest Path Calculations Logic Gate Level Cg to #N #M Drive #NS N #NS P WN WP (H. C) (S) (L) Cg of gate 1 Mux-DFF Slave Nand 17. 1 1 2 1. 96 1. 63 3. 9 3. 45 1. 96 1. 63 5. 99 1 a Mux-DFF Slave Latch 5. 99 2 2 3. 96 6. 8 3. 9 6. 85 3. 96 6. 8 18. 3 1 b Mux-DFF Master Nand 17. 1 1 2 3 2. 55 3. 9 3. 45 1. 96 1. 63 5. 99 1 c Mux-DFF Master Latch 5. 99 2 2 3. 96 6. 8 3. 9 6. 85 3. 96 6. 8 18. 3 2 Inveter 20 1 1 1. 5 2. 7 1. 95 3 8. 43 2 a Mux (AOI 22) 8. 43 6 6 2 2 4. 31 7. 49 2. 85 4. 65 20. 1 3 Inveter 40 1 1 2. 86 5. 14 3 6 13. 6 3 a MUX (AOI 22) 13. 6 6 6 2 2 3. 46 5. 99 2. 25 3. 9 16. 1 4 Inveter 32 1 1 2. 32 4. 17 3 6 11. 1 4 a MUX (AOI 22) 11. 1 6 6 2 2 3. 45 6. 15 16. 4 5 Superbuffer 17. 8 4 4 2 2 3. 7 6. 36 12 6 inverter 1 240 1 1 26. 7 49. 2 7

Schematic 8

Layout 9

Verification 10

Simulations 11

Cost Analysis • Estimate how much time you spent on each phase of the project – verifying logic (40 hours) – verifying timing (10 hours) – Layout (many hours 100+ hours) – Post extracted timing (3 hours) 12

Lessons Learned • Start early • Using the excel sheet to calculate Wn & Wp • Make sure to use the correct devices for layout if the same type of parts are used more than once. • Plan device schematic carefully and attack it part by part making sure that it works with the other parts of the circuit • Problems will always come up during LVS no matter how carefully it was wired together. • Because a device passes DRC does not mean that it will pass LVS when placed in layout 13

Summary • Barrel shifters have the ability to shift data words in a single operation over standard shift left or shift right registers that utilize more than one clock cycle. • Barrel shifters will continue to be used in smaller devices because it has a speed advantage over software implemented ones. 14

Acknowledgements • • • Cadence Design Systems Synopsys Prof. Parent David Flores Junghoon Kang 15