Design of a Near Threshold Low Power DLL

Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication Mehdi Sadi, Italo Armenti

Outline 1. Introduction and Motivation 2. Background 3. Our Works and simulations 4. Conclusions and Future Works

Introduction and Motivation �Delay Locked Loops (DLL) are extensively used for multiphase clock generation in So. C and in clock and data recovery circuits. �DLL`s counterpart Phase Locked Loops(PLL) suffer from instability due to PVT variation and noise. �Very few researchers have looked into the effect of voltage scaling on DLL performance.

Design Challenges Design challenges when voltage supply is scaled down �Appropriate device sizes in the critical path, � Ensuring correct duty cycle at output frequency. � Keeping static phase error within bounds.

Background (Mesgardazeh et. al) �Possible to redesign with reduced components but same performance at operating frequency.

Block diagram

Phase Detector � C 2 MOS DFF with Reset option. � Critical path devices are sized to ensure faster charging and discharging at the desired frequency range. Freq Minimum Resolution Power(u. W) 1 GHz 45 p 40 700 M 55 p 39. 88 500 M 55 p 39. 63 200 M 55 p 39. 63 100 M 55 p 39. 62

Delay Line � Binary weighted switched capacitors control the delay per stage.

** Delay Line Design �Delay per stage, �At lock in condition The switching voltage should be adjusted at VDD/2 to avoid duty cycle error.

Counter � 8 bit binary up down counter with reset and hold options. � The counter is power and clock gated to reduce power when the clock phases are aligned. � During Sleep mode the counting states are held in a latch. Gating Effect Started Power without gating = 9. 1 u. W Power with gating = 2. 72 u. W 70 % Power saved with gating

Edge Combiner � XOR Gate Based Edge Combiner. Generates 4 times the reference frequency � To ensure proper duty cycle the Devices in the critical path must be sized properly. Sizing also depends on operating frequency range.

Full Waveform

Process Variation Process Corner Static Phase error (ps) Lock in time at 200 MHz TT 50 50 cycles SS 55 55 cycles FS 47 50 cycles SF 45 50 cycles (also duty cycle mismatch) FF 45 60 cycles

Performance This work IEEE Tran 08 JSSC 09 VLSI Symp 07 Type All Digital Process 45 nm 0. 35 um 90 nm 0. 13 um Supply 0. 7 V 3. 3 V 1 V 1. 2 V Frequency Range Static Phase Error Lock in time 80 MHZ - 200 MHz 4 -200 MHz 2 GHz 1. 6 GHz N/A N/A Between 28 to 110 Cycles 16 cycles N/A Power 120 u. W 17 m. W 6 m. W 55 ps

Conclusion �We have designed a ultra low power all digital DLL operating at 80 -200 MHz with 0. 7 V supply and 120 u. W. �The DLL can be scaled down to operate at further low voltage by adjusting the critical path device widths

Thank You