Design of a High Resolution TDC Module for

Design of a High Resolution TDC Module for Micro. TCA based on the GPX ASIC H. Kleines, A. Ackens, P. Kämmerling, P. Wüstner, M. Drochner, W. Erven Zentralinstitut für Elektronik, Forschungszentrum Jülich, Germany • PANDA: detector system at future FAIR facitility in Darmstadt • PANDA Straw Tube Tracker requires TDC development • PANDA DAQ will be based on ATCA • Micro. TCA: for lab systems + cost-efficient development environment => Develop TDC module for Micro. TCA Zentralinstitut für Elektronik (ZEL)

GPX ASIC (in I-mode) • Developed by acam messelectronic gmbh as “successor” of F 1 (from COMPASS experiment) • 8 channels, LVTTL Inputs • 81 ps resolution (typ. ) • Double pulse resolution: 5, 5 ns • Depth of Hit-Fifo: 32 • 40 MHz continuous rate (over all channels) • Existing Experience from Zentralinstitut für Elektronik (ZEL) WASA@COSY

µTCA TDC Module Design Start + clock 32 STOP DAC, … ECL/LVPECL/LVDS to LVTTL GPX 4 div. Signals GPX 3 GPX 2 GPX 1 PIC 32 XC 5 VLX 30 T I 2 C PCIe (4 Lanes) Gb. E (Option) T. CLOCK A, B • Double width, compact size AMC module => 32 Channels • 4 lane PCIe according to AMC. 1 in fat pipe on the basic side • Xilinx XC 5 VLX 30 T FPGA => embedded PCIe endpoint • MMC implementation will be based on Microchip PIC 32 MX 460 F 512 L microcontroller Zentralinstitut für Elektronik (ZEL)

Status • Layout finished and PCB available • FPGA code has still to be developed • Major issue: Module Management Controller (MMC) implementation (based on IPMI over I 2 C) • Development systems have been ordered – Crates: from Schroff and ELMA – CPUs: ADLINK and Emerson – MCHs: NAT and Emerson Zentralinstitut für Elektronik (ZEL)