Design Methodology HDL Design Methodology HDL Hardware Description

HDL - Hardware Description Language ¡ VHDL & Verilog (IEEE standard) l l l

HDL vs. other Language (1) ¡ Parallel & sequence block concept B 1 A

HDL vs. other Language (1 a) ¡ block concept 1. Combination circuit function →

HDL vs. other Language (2) ¡ Timing concept A A C B C

HDL vs. other Language (3) ¡ Event trigger concept A B C A C

HDL vs. other Language (3 a) ¡ Synchronous design concept Input_N B Clock Input_N

HDL vs. Finite state machine Idle_st A 1_i FSM 1_st A 1_o A 2_i

Verilog HDL – Level Property Transistor Level (Model) ¡ Gate Level Model (Model) ¡

Electronics System Level Design ¡ System C & System Verilog ( ESL ) l

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Design Methodology & HDL 黃俊傑

Design Methodology

HDL - Hardware Description Language ¡ VHDL & Verilog (IEEE standard) l l l l Define Specification Design Description Function Verification Logic synthesis Gate-Level Netlist Verification Place and Routing Post Layout Verification

HDL vs. other Language (1) ¡ Parallel & sequence block concept B 1 A B 2 B 3 C

HDL vs. other Language (1 a) ¡ block concept 1. Combination circuit function → without F/F 2. Sequence circuit function → with F/F ( memory characteristic ) l Mix (1) and (2) into block concept F/F Input C Output

HDL vs. other Language (2) ¡ Timing concept A A C B C

HDL vs. other Language (3) ¡ Event trigger concept A B C A C D D

HDL vs. other Language (3 a) ¡ Synchronous design concept Input_N B Clock Input_N Clock Output

HDL vs. Finite state machine Idle_st A 1_i FSM 1_st A 1_o A 2_i FSM 2_st A 2_o A 3_i FSM 3_st A 3_o Done

Verilog HDL – Level Property Transistor Level (Model) ¡ Gate Level Model (Model) ¡ Register Transfer Level ¡ Behavioral Level ¡

Electronics System Level Design ¡ System C & System Verilog ( ESL ) l l l l Define Specification (+) Design Description (+) Function Verification (+) Logic synthesis (-) Gate-Level Netlist Verification (-) Place and Routing (-) Post Layout Verification (-)