Design for Testability Sungho Kang Yonsei University Outline

Design for Testability Sungho Kang Yonsei University

Outline l l l Introduction Testability Measure Design for Testability Ad-Hoc Testable Design Conclusion CS&RSOC YONSEI UNIVERSITY 2

Merging Design and Test l Introduction Design and Test become closer CS&RSOC YONSEI UNIVERSITY 3

Design and Test l Introduction Design process CS&RSOC YONSEI UNIVERSITY 4

Testability Measures l Testability § § Inherent property of the circuit based on the circuit topology Probability that a fault is detected by a random vector Function of controllability and observability Controllability ÄAbility to establish a specific signal value at each node in the circuit by setting values on the circuit inputs § Observability ÄAbility to determine the signal value at any node in a circuit by controlling primary inputs and observing its outputs l Objective § Estimate testability § Provide guidance for redesign § Provide guidance in search process of test generation l Measures should be computationally simple CS&RSOC YONSEI UNIVERSITY 5

What Designers Want to Know l Testability Will this device require an inordinate amount of time, level of effort, and/or test length in order to provide acceptable testing? § Require general information about design l What are the problem areas in the design where a modification can ease the testing problem? § Require detailed information § Testability measures might be useful § Detailed information may be useful to the above question CS&RSOC YONSEI UNIVERSITY 6

SCOAP Testability l Sandia Controllability and Observability Analysis Program Compute relative complexity to control and observe l Combinational Node l § Primary input or a combinational standard cell output node l Sequential Node § Output node of a sequential standard cell CS&RSOC YONSEI UNIVERSITY 7

SCOAP l l Testability 6 Numbers for Each Node, N CC 0(N): combinational 0 -controllability § minimum # of combinational nodes to set node N to 0 l CC 1(N): combinational 1 -controllability § minimum # of combinational nodes to set node N to 1 l SC 0(N): sequential 0 -controllability § minimum # of sequential nodes to justify 0 to node N l SC 1(N): sequential 1 -controllability § minimum # of sequential nodes to justify 1 to node N l CO(N): combinational observability § # of combinational nodes between N and PO and minimum # of combinational nodes to propagate a signal value on N to PO l SO(N): sequential observability § # of sequential nodes between N and PO and minimum # of sequential nodes to propagate a signal value on N to PO CS&RSOC YONSEI UNIVERSITY 8

SCOAP l Initial Values for PIs and POs § § § § l Testability CC 0(X) CC 1(X) SC 0(X) SC 1(X) CO(X) SO(X) PI 1 1 0 0 PO 0 0 Buffers and Inverters § § § § Buffers CC 0(Y) CC 0(X)+1 CC 1(Y) CC 1(X)+1 SC 0(Y) SC 0(X) SC 1(Y) SC 1(X) CO(Y)+1 SO(X) SO(Y) CS&RSOC Inverters CC 1(X)+1 CC 0(X)+1 SC 1(X) SC 0(X) CO(Y)+1 SO(Y) YONSEI UNIVERSITY 9

SCOAP l Testability Y = AND (X 1, X 2) § § § CC 0(Y) = min[CC 0(X 1), CC 0(X 2)] + 1 CC 1(Y) = CC 1(X 1) + CC 1(X 2) + 1 SC 0(Y) = min[SC 0(X 1), SC 0(X 2)] SC 1(Y) = SC 1(X 1) + SC 1(X 2) CO(X 1) = CO(Y) + CC 1(X 2) + 1 SO(X 1) = SO(Y) + SC 1(X 2) CS&RSOC YONSEI UNIVERSITY 10

SCOAP l Testability Fanout § CC 1(Y) = CC 1(X) § CC 1(Z) = CC 1(X) § CO(X) = min [CO(Y), CO(Z)] CS&RSOC YONSEI UNIVERSITY 11

SCOAP l Testability Example § § § § § CC 0(A) = CC 1(A) = CC 0(B) = CC 1(B) = CC 0(C) = CC 1(C) = 1 CC 0(D) = min [CC 0(A), CC 0(B)] + 1 = 2 CC 1(D) = CC 1(A) + CC 1(B) + 1 = 3 CC 0(E) = CC 0(D) + CC 0(C) + 1 = 4 CC 1(E) = min [CC 1(C), CC 1(D)] + 1 = 2 CO(E) = 0 CO(D) = CO(E) + CC 0(C) + 1 = 2 CO(C) = CO(E) + CC 0(D) + 1 = 3 CO(A) = CO(D) + CC 1(B) + 1 = 4 CO(B) = CO(D) + CC 1(A) + 1 = 4 CS&RSOC YONSEI UNIVERSITY 12

SCOAP l Testability Tree § Good estimate l l Problem in reconvergent fanout Optimistic Error § Want 3/ l Pessimistic Error § Want 2/2 CS&RSOC YONSEI UNIVERSITY 13

Limitations of Testability Measures l l Testability All testability measure have similar simplifying assumptions so that all results are estimates Involves the restricted information source (only circuit topology) Faults which are difficult to test cause problems Testability data provide a relatively poor indication of whether or not an individual fault will be detected by a given test CS&RSOC YONSEI UNIVERSITY 14

Design for Testability l Design for Testability Difficulty in ATPG § Not effective for large sequential circuits l Advantages § Test generation is easy § High quality testing l Disadvantages § Area overhead § Timing overhead CS&RSOC YONSEI UNIVERSITY 15

Classification of DFT l Design for Testability Ad-Hoc Design § Initialization § Adding extra test points § Circuit partitioning l Structured Design § Scan design ÄScan Path ÄLevel Sensitive Scan Design ÄRandom Access Scan § Boundary Scan § Built-in Self Test CS&RSOC YONSEI UNIVERSITY 16

Ad Hoc Techniques l l l Ad-Hoc Techniques which can be applied to a given product, but are not directed at solving the general problem Cost is lower than that of structured approaches (Scan, BIST, etc. ) The job of doing test generation and fault simulation are usually not as simple or as straightforward CS&RSOC YONSEI UNIVERSITY 17

Test Points l l l Ad-Hoc Employ test points to enhance controllability and observability Large demand on extra I/O pins Example CS&RSOC YONSEI UNIVERSITY 18

Test Points l Ad-Hoc Multiplexing monitor points CS&RSOC YONSEI UNIVERSITY 19

Test Points l Ad-Hoc Use demultiplexer and latch register to implement control points CS&RSOC YONSEI UNIVERSITY 20

Test Points l Ad-Hoc Time sharing I/O ports CS&RSOC YONSEI UNIVERSITY 21

Test Points l Candidates for control points § § § l Ad-Hoc Control, address, and data bus lines on bus structured designs Enable/hold inputs to microprocessors Enable and read/write inputs to memory devices Clock and preset/clear inputs to memory devices Data select lines to multiplexers and demultiplexers Control lines on tristate devices Candidates for observation points § § § Stem lines associated with signals having lots of fanouts Global feedback paths Redundant signal lines Outputs of logic devices having many inputs Outputs from state devices Address, control, and data buses CS&RSOC YONSEI UNIVERSITY 22

Initialization l l Ad-Hoc Design circuits to be easily initializable Initialization § Process bringing a sequential circuit into a known state at some known time § Circuits requiring some clever initialization sequence should be avoided l Flip-flop with explicit clear § Use explicit clear to all FFs CS&RSOC YONSEI UNIVERSITY 23

Oscillators and Clocks l l Ad-Hoc Disable internal oscillators and clocks during test Example § A = 0 and B : Test input CS&RSOC YONSEI UNIVERSITY 24

Partitioning l Ad-Hoc Partitioning shift registers into smaller units CS&RSOC YONSEI UNIVERSITY 25

Partitioning l Ad-Hoc Split large counters CS&RSOC YONSEI UNIVERSITY 26

Partitioning l l Ad-Hoc Partitioning large circuits into small subcircuits to reduce test generation cost Example § T 1=0 T 2=0 : Normal Mode § T 1=0 T 2=1 : Test C 1 § T 1=1 T 2=0 : Test C 2 CS&RSOC YONSEI UNIVERSITY 27

Avoid Use of Redundant Logic l l l Design Rule If a redundant fault occurs, it may invalidate some test for non-redundant faults Such faults cause difficulty in calculating fault coverage Much test generation time can be spent CS&RSOC YONSEI UNIVERSITY 28

Avoid Global Feedback Paths l l l Design Rule Provide logic to break global feedback paths Asynchronous circuits other than latches should be avoided when possible Avoid combinational feedback loop CS&RSOC YONSEI UNIVERSITY 29

Avoid Gated Clock l Design Rule Make sure EN settles before CLK changes § Or redesign the circuit as follows CS&RSOC YONSEI UNIVERSITY 30

Bypass Counters CS&RSOC Design Rule YONSEI UNIVERSITY 31

Avoid Internal Pulse Generator l Design Rule All internal pulse or clock generators should be isolated during test CS&RSOC YONSEI UNIVERSITY 32

Avoid Cross-coupled NAND/NOR l Design Rule Add logic to make each cross-coupled NAND/ NOR gate behave as a transparent buffer during test CS&RSOC YONSEI UNIVERSITY 33

Avoid Bus Floating l Design Rule Make sure each tristate bus has one pullup register, pulldown register or bus holder CS&RSOC YONSEI UNIVERSITY 34

Avoid Potential Bus Contention l Design Rule Make sure only one tristate gate is selected at a time CS&RSOC YONSEI UNIVERSITY 35

Easily Testable Circuits l l Testable Design Aimed at developing design techniques that start with a functional specification and results that are easy to test Properties § § § Small test sets No redundancy Tests can be found without much extra work Tests can be easily generated Faults should be locatable to the desire degree CS&RSOC YONSEI UNIVERSITY 36