DESIGN FOR MANUFACTURABILITY DEPARTMENT OF ELECTRICAL COMPUTER ENGINEERING

DESIGN FOR MANUFACTURABILITY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

DUMMY POLY Severe distortion Reduced distortion

DUMMY POLY Dummy gates for increased manufacturability

DUMMY GATES Dummy gate Active gate Dummy gate Unused area Dummy gates induce spared silicon area Active gate

DUMMY GATES • Some nano-CMOS require 2 dummy gates per cell (Intel 14 -nm) • Shared dummy gates reduce the cell area (Intel 10 -nm) 10 nm technology leadership, KAIZAD MISTRY, TECHNOLOGY AND MANUFACTURING DAY, 2017

DUMMY GATES Active gate Shared Dummy gate Active gate

DOUBLE PATTERNING For pitch lower than 80 nm (M 2 -M 8): simple patterning For pitch lower than 80 nm (M 1 -M 2): double patterning

DOUBLE PATTERNING Initial M 1 layer 6 λ minimum pitch Bridge After fabrication in single patterning Open

DOUBLE PATTERNING 66 nm pitch M 1 patterns need double patterning First patterning Second patterning

FINFET MANUFACTURABILITY • Fins should be aligned and horizontal, regular pitch 6 (1+5) • Non-aligned fins may lead to gate distortion and current performance spread Ion Ioff

FINFET MANUFACTURABILITY • Gates should be aligned and vertical, regular pitch with 8 minimum (2+6)

STUDENT DESIGNS Nearly manufacturable SRAM project by Master students INSA, 2016 Not manufacturable ALU project by Master students INSA, 2016