Design Codesign of Embedded Systems Modules Hierarchy in
Design & Co-design of Embedded Systems Modules & Hierarchy in System. C Maziar Goudarzi 2005 Design & Co-design of Embedded Systems
Today Program z Modules in System. C z Hierarchical Design in System. C 2005 Design & Co-design of Embedded Systems 2
Why Modules? z. Advantages y. Building Block in Design Hierarchy y. Team Work y. Design Encapsulation y. Design Re-use 2005 Design & Co-design of Embedded Systems 3
Parts of a Module z. Ingredients y. Module Ports y. Module Signals y. Internal Data Storage y. Processes y. Module Constructors 2005 Design & Co-design of Embedded Systems 4
General Syntax for Module Definition Port mode SC_MODULE( module_name ) { sc_in< bool > in; sc_out< int > out; sc_inout< float > inout; Port type sc_signal< char > a. Signal; long l; // internal data storage void process() {. . . } // processes SC_CTOR( module_name ) {. . . } }; 2005 Design & Co-design of Embedded Systems 5
What is SC_MODULE? z Defined in <System. C>includekernelsc_module. h #define SC_MODULE(user_module_name) struct user_module_name : sc_module class sc_module: public sc_object{. . . }; 2005 Design & Co-design of Embedded Systems 6
Ports z Port modes y sc_in< > y sc_out< > y sc_inout< > y Specific to clock ports (only for backward compatibility) xsc_in_clk xsc_out_clk xsc_inout_clk y Actually: (look at <systemc>/include/communication/sc_clock_ports. h ) xtypedef sc_in<bool> sc_in_clk; xtypedef sc_inout<bool> sc_inout_clk; xtypedef sc_out<bool> sc_out_clk; 2005 Design & Co-design of Embedded Systems 7
Signals z Signal y Used to connect ports of lower-level modules y Correspond to wires y Unlike ports, no mode (in, out, inout) required x. Bi-directional transmission possible x. Actual direction depends on the connecting ports y Syntax x sc_signal< signal_type > signal_name; 2005 Design & Co-design of Embedded Systems 8
Connecting Ports & Signals z. Note: when connecting ports using signals y. Type of signals and ports must match xsc_in< int > int. Input; xsc_signal< int > int. Signal; z. Port mapping y. Positional port mapping y. Named port mapping 2005 Design & Co-design of Embedded Systems 9
Positional Port Mapping // filter. h #include "systemc. h" #include "mult. h" #include "coeff. h" #include "sample. h" SC_MODULE(filter) { sample *s 1; coeff *c 1; mult *m 1; sc_signal< int > q, s, c; SC_CTOR(filter) { s 1 = new sample ("s 1"); (*s 1)(q, s); Port mapping 2005 } } Module instantiation // sample. h SC_MODULE(sample) { c 1 = new coeff ("c 1"); (*c 1)(c); sc_in<int> din; sc_out<int> dout; . . . m 1 = new mult ("m 1"); (*m 1)(s, c, q); Design & Co-design}; of Embedded Systems 10
Positional Port Mapping (cont’d) z Positional port mapping y. Ports are connected in the same order as in the module definition y. Orders and number of ports MUST match in the definition and in the instantiation y. One C++ statement to map all ports y. Advantage x. Compactness x. Good when only having a few ports y. Disadvantage x. Less readability x. Error prone 2005 Design & Co-design of Embedded Systems 11
Named Port Mapping #include "sample. h“ SC_MODULE(filter) { sample *s 1; coeff *c 1; mult *m 1; sc_signal< int > q, s, c; SC_CTOR(filter) { s 1 = new sample ("s 1"); s 1 ->dout(s); s 1 ->din(q); c 1 = new coeff ("c 1"); c 1 ->out(c); // sample. h SC_MODULE(sample) { sc_in<int> din; m 1 = new mult ("m 1"); sc_out<int> dout; m 1 ->a(s); . . . m 1 ->b(c); m 1 ->q(q); Design & Co-design}; of Embedded } 2005 Systems }; 12
Named Port Mapping (cont’d) z. Named port mapping y. Ports can be connected in any order y. One C++ statement to map each port y. Advantage x. More readability x. Less possibility for errors y. Disadvantage x. More verbose 2005 Design & Co-design of Embedded Systems 13
Port Mapping: Another Positional Mapping Style // filter. h #include "systemc. h" #include "mult. h" #include "coeff. h" #include "sample. h" SC_MODULE(filter) { sample *s 1; coeff *c 1; mult *m 1; sc_signal< int > q, s, c; SC_CTOR(filter) { s 1 = new sample ("s 1"); (*s 1)(q, s); SC_CTOR(filter) { s 1 = new sample ("s 1"); (*s 1) << q <<s; c 1 = new coeff ("c 1"); (*c 1)(c); 2005} } c 1 = new coeff ("c 1"); (*c 1) << c; m 1 = new mult ("m 1"); (*m 1)(s, c, q); (*m 1) << s << c << q; Design & Co-design of Embedded Systems } } 14
Hierarchical Design z Key to implementing complex designs y. Divide and conquer z Two approaches y. Bottom-up design y. Top-down design 2005 Design & Co-design of Embedded Systems 15
Hierarchical Design (cont’d) z. Two basic styles for connecting modules y. One module connected to the other one x. In the same level of hierarchy x. Example • the previous filter example: sample, coeff, and mult modules all in the same level of hierarchy y. One module inside the other one x. Hierarchical design x. Example: A register consisting of several DFFs 2005 Design & Co-design of Embedded Systems 16
Hierarchical Modules Example z. Register Module d Register q DFF DFF clk 2005 Design & Co-design of Embedded Systems 17
Hierarchical Modules Example (cont’d) #include "dff. h“ d #define REG_WIDTH 10 SC_MODULE(reg) { sc_in<bool> d[REG_WIDTH]; sc_in<bool> clk; sc_out<bool> q[REG_WIDTH]; Register DFF DFF q clk DFF *ff[REG_WIDTH]; SC_CTOR(reg) { for(int i=0; i<REG_WIDTH; i++) { ff[i] = new DFF( itoa(i, NULL, 10) ); ff[i]->d(d[i]); Direct port-to-port ff[i]->q(q[i]); ff[i]->clk(clk); connection (no signal) } Design & Co-design of Embedded } 2005 }; Systems 18
Rules for Connecting Ports z. In hierarchical design y. Port modes must match xsc_in<> to sc_in<> xsc_out<> to sc_out<> xsc_inout<> to sc_inout<> 2005 Design & Co-design of Embedded Systems 19
Parts of a Module (cont’d) z. Ingredients y. Module Ports y. Module Signals y. Internal Data Storage y. Processes y. Module Constructors 2005 Design & Co-design of Embedded Systems 20
Internal Data Storage: Counter with Synchronous-Load SC_MODULE(counter) { sc_in<bool> load; sc_in<int> din; sc_in<bool> clock; sc_out<int> dout; int count_val; void counter: : count_up() { if (load) count_val = din; else count_val++; dout = count_val; } void count_up(); SC_CTOR(counter) { SC_METHOD(count_up); sensitive_pos << clock; } }; 2005 Design & Co-design of Embedded Systems 21
Internal Data Storage (cont’d) z. Can be any C++ type or user-defined type z. Visible outside the module y. Remember: SC_MODULE is a C++ struct y. NOTE: Although C++ allows it, DO NOT change values of internal variables from outside a module 2005 Design & Co-design of Embedded Systems 22
Process z Implement the real functionality of the module z Sensitivity list: y List of ports that this process is sensitive to z Registered with “System. C Simulation Kernel” at run-time y Name of the process + its sensitivity list y Place & time: at module instantiation time (when the constructor is called) z Called by “System. C Simulation Kernel” y whenever one of the ports in the “sensitivity list” changes value z Executes sequentially until return() or wait() 2005 Design & Co-design of Embedded Systems 23
Process (cont’d) // dff. h #include "systemc. h" SC_MODULE(dff) { sc_in<bool> din; sc_in<bool> clock; sc_out<bool> dout; void doit() { dout = din; } SC_CTOR(dff) { SC_METHOD(doit); sensitive_pos << clock; } }; 2005 Design & Co-design of Embedded Systems 24
Module Constructor z Register module Processes, and their sensitivity list with “System. C Kernel” z Create and initialize “Internal Data Structures” of the module z Initialize Internal Data Storage z An “instance name” is passed to the constructor at instantiation time y. Each instantiated module (even from the same SC_MODULE type) can have its own name y. Helps in reporting debug, error, and information messages from the module 2005 Design & Co-design of Embedded Systems 25
Module Constructor (cont’d) // ram. h #include "systemc. h" SC_MODULE(ram) { sc_in<int> addr; sc_in<int> datain; sc_in<bool> rwb; sc_out<int> dout; int memdata[64]; // local memory storage int i; void ramread(); void ramwrite(); SC_CTOR(ram){ SC_METHOD(ramread); sensitive << addr << rwb; Process declaration SC_METHOD(ramwrite) sensitive << addr << datain << rwb; for (i=0; i++; i<64) memdata[i] = 0; } }; 2005 Design & Co-design of Embedded Systems 26
What we learned today z. Modules in System. C and its ingredients z. Hierarchical Design in System. C z. System. C ver. 2. 0 User’s Guide y. Chapters 1 2 3 2005 Design & Co-design of Embedded Systems 27
Assignment 1 z. Design a T-FF using only basic gates (i. e. , AND, OR, NOT, NAND, NOR gate) and hierarchical design (top-down or bottomup) z. Write a complete test bench for your T-FF and compile and simulate your model. z. Due date: Tuesday, Mehr 26 th 2005 Design & Co-design of Embedded Systems 28
Other Notes z Deadline for 1 -page document y Your partner(s) for course project y The definition of the project y Rough schedule 2005 Design & Co-design of Embedded Systems 29
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