Design and Implementation of GPS Receiver Module 6

Design and Implementation of GPS Receiver (Module 6) In current competitive environment, with product life cycles measured in months, getting it right the first time takes on new importance. Designs are increasingly complex and often comprise hybrid technologies including RF, high-speed signal processing (50 -200 mega samples per second as well as lower speed signal processing and control. This module contains the description of the design and implementation of the GPS receiver. First the implementation of a GPS simulator will be described followed by the description of the techniques for getting real GPS signals and an analysis of the sampled data. Acquisition techniques and tracking loops will be also discussed. 1

Review of GPS Receiver • The GPS system has been fully operational with 24 satellites in its constellation. • The fundamental concept of using code-division multiple access (CDMA) for time-delay measurement (yielding range) while allowing all satellites to share the same carrier frequency (1. 57542 GHz for civilian access) has not changed in the past 30 years. • Each GPS satellite uses a unique 1, 023 -chip orthogonal code (Gold code) to spread the low-speed binary phase shift keying (BPSK, 20 ms per bit) navigation data bitstream. The chipping clock rate is 1. 023 MHz, and therefore the sequence of 1, 023 chips repeats every millisecond. • The GPS receiver generates a local copy of the same Gold code, which is then cross-correlated with the incoming signal. When the receiver code phase aligns with the incoming signal code phase, there is a +30 d. B improvement in the SNR (10 ×log 10(1023)), and the BPSK navigation bitstream may then be easily detected. 2

Model-based Design • Studies have shown that defects are most often introduced at the beginning of any design. Before adding more detail to the model, it is necessary to verify that it truly implements a GPS receiver. • The concept of model-based design is quite simple. First, create a functional implementation independent model of the system. This is an “executable specification, ” a model that forms the basis of all that is to follow. Once the model is verified to achieve system objectives, further details can be incorporated. • The MATLAB language is becoming increasingly popular in test and measurement applications. The Instrument Control Toolbox option for MATLAB can communicate with virtually any instrument that has a hardware interface. • Several test and measurement vendors have integrated MATLAB into their instruments. For example the spectrum analyzer from many vendors can capture data into MATLAB with a single mouse click. 3

A top-level view of a GPS system, including a transmitter with timing error, channel model with Doppler, and a receiver with timing and Doppler de-rotation loops. 4

GPS Signal Simulation Flow Diagram For each satellite and multipath components Baseband signal generator Phase and amplitude variations may be added Sample rate, C/A and/or P code L 1 or L 2, etc. Antenna pattern scintillation Sum signals Add other signals Jamming and interference Signal from antenna output Receiver front end Output signal 5

GPS Signal Simulation • The GPS signal simulator is required to dramatically reduce the need for expensive and time-consuming field trials when testing, evaluating or qualifying GPS receiver equipment and the developed GPS application system. • In order to simulate the signal, few properties of a GPS signal should be defined. – – – PRN Doppler Code Phase P(Y) Code Data Bits Signal Strength 6

Simulink Simulation 7

C/A Code Generation • • See the source of the C/A code in the diagram (blue). This oscillator produces a squared pulse with a frequency of 1. 023 MHz corresponding to the chipping rate of the C/A code. The conventional C/A code generator consists of two 10 -stage Linear Feedback Shift Register (LFSR) binary sequence generators and a selector for choosing the proper output taps from the register, and a final modulo-2 combiner. The counter is designed to count from 0 to 1022, referring to the 1023 chips in the PRN sequence. The counter increases its value each time a falling edge occurs in the pulse signal, that is with a frequency of 1. 023 MHz. The following figure shows the output from the counter. 8

Navigation Data Generation • See the orange boxes in the Figure. • The bit rate of the binary navigation data sequence is 50 Hz. • In the simulator, the generator signal to the navigation data sequence is obtained from the output of the counter in the C/A part. • To obtain a 50 Hz signal from the signal supplied by the C/A counter, the first block in the navigation data part is a counter, which increases its value on every falling edge of the input signal. The counter resets when it reaches 20, that is every 20 ms corresponding to 50 Hz. • The next block is a counter. It works in the same way as the counter in the C/A part. It increases its output value with every falling edge of the input signal, and it resets at the end of the period. • The period is set to be one navigation data frame corresponding to 1500 bits. 9

P Code Generation • See the yellow boxes in the Figure. • The P code should be simulated as a squared pulse alternating between -1 and 1. • In the second block of the P code part, this signal is combined with the navigation data sequence. • The carrier generation part is almost similar to the carrier generation in the C/A part. The only difference is that the VCO has a 90 o phase shift compared to the other VCO. • The result of this is that the P code VCO generates a sine wave compared to the C/A VCO’s cosine wave. • The combined P code and navigation data signal is BPSK modulated onto the carrier in the multiplication block. • The final block is the gain block. It decreases the modulated P code signal by 3 d. B. 10

Combining the Signal Components • The last part of the GPS signal simulator is located at the right most part of the figure. • The two modulated codes are combined resulting in a complete GPS signal. • The two components are added together as in-phase and quadrature components of the final signal. • The last part is the addition of the noise. See the green box. • The amount of noise is selected from an input to the simulation. The resulting noise from the noise generator is added to the GPS signal. 11

Upper Level Implementation The upper level can be designed. It implements the different satellites needed in the simulation and selects the file in which the simulated data should be saved. The following figure shows an example of how the upper level of the signal simulator could be implemented. The simulator contains four different satellites. Each of the satellites have different values of SVN, PRN code phase. 12

Obtaining Real GPS Data • The GPS simulator is used in the initial development of the signal acquisition and tracking algorithms. • When the algorithms prove to be working on the simulated data, they should be tested on real navigation GPS data. • Some physical conditions can not be simulated perfectly. Theses are: – Atmospheric disturbances which affect the signal on their path. – Other systems transmitting in the radio frequencies located close to the GPS frequencies. – Physical obstacles located near the receiving antenna. • Finally, we will say that algorithms should be designed so they eventually can be used in the working GPS receiver. 13

Needed Hardware GPS antenna RF front end A/D converter Computer Antenna Analog IF signal Analog RF signal RF front-end A/D converter Computer Sampling clock Digital IF signal 14

Example RF front end 15

Down Conversion • The front end uses a local oscillator (LO) with a frequency of 11. 999 MHz. This frequency is used for the two-step-down-conversion. It is also supplied as an output of the front-end to be used as a sampling clock. • Down conversion is performed in two steps: • The first down-conversion from the RF frequency involves 128 times injection of the LO. That is, a LO signal with a frequency of f. Lo=128× 11900 MHz =1535. 782 MHz. • L 1 frequency is located at 1575. 42 MHz. Accordingly the first IF (IF 1) is placed at a frequency of 1575. 42 – 1535. 782 = 39. 548 MHz. • The image frequency band is located at 1575. 42 – 2 × 39. 548 = 1496. 324 MHz. 16

• The second-down conversion from IF 1 to the final IF involves a 3 times injection of the LO. That gives an LO frequency of 3 × 11900 = 35997 MHz. • The resulting IF is placed at a frequency of 39548 – 35997 = 3. 551 MHz. • In this down-conversion, the image frequency band is located at 39548 -2× 3. 551 = 32446 MHz. • None of the two image frequencies are located in frequency bands with high power signals, like for example radio signals, TV signals or cellular signals. 17

Amplification • The amplification of the GPS signals concern the output amplifier of the front-end. This amplifier is driven into saturation. That is, it tries to amplify the input to a larger output that it can actually provide. This causes clipping in amplitude. An over-saturated amplifier actually distorts the signal. • Another result of using an over-saturated amplifier on the output is, that the signal magnitude is always sufficiently high to be detected by an A/D converter. • If the amplifier was designed to avoid clipping it might have been necessary to combine it with an automatic gain control (AGC), which ensures that the signal is always detected by the A/D converter. 18

Filtering • The necessity of filtering have been described in previous lecture. It was shown what influence image frequencies caused by downconversion could have if they were not removed by filtering. • The first step in the down-conversion demands a filter to remove the frequencies around 1496. 324 MHz. • The only frequencies that should be preserved by the filter are located at 1575. 42 MHz with a bandwidth of approximately 2 MHz. • This gives a quite wide margin of approximately 80 MHz to the transition band of the filter. 19

• The second step in the down-conversion demands a filter to remove the frequencies around 32. 446 MHz. In this case the signal components that should be preserved are located in the frequency band 39. 548 ± 2 MHz. This gives a smaller margin of approximately 5 MHz to the transition band. • Another filter is implemented to avoid aliasing when the signal is sampled. An anti-aliasing filter should remove possible signal components with frequencies larger than half the sampling frequency employed in the A/D converter. The sampling frequency is around 12 MHz, so the anti-aliasing filter should remove all signal components with frequencies larger than 6 MHz. • The front end includes a 6 th order Butterworth filter on the output with a -3 d. B band-width of ± 1. 8 MHz used at the IF of 3. 551 MHz. So the output is attenuated 3 d. B at 5. 3 MHz. 20

A/D Converter • The most important demand for an A/D converter is that the sampling frequency should be at least twice the highest frequency in the input signal. In this case the highest frequency of the IF signal is • When sampling with a frequency of fs = 11. 999 MHz this demand is completely fulfilled 21

Requirements to the A/D Converter • Minimum sampling rate: The A/D converter should be able to sample the analog input signal with a frequency of 11. 999 MHz, which is the frequency supplied by the RF front-end. • External sampling clock: It should be possible to supply an external sampling clock to the A/D converter. The external sampling clock is usually provided by the RF front end. • Amplitude resolution: The required minimum amplitude resolution is 1 bit. This requirement should be manageable by all A/D converters. • Connection to PC: It should be possible to connect the A/D converter to a PC which should be able to either process the data in real time or save it to file. • Acquisition: The A/D converter should be able to make continuous acquisition. This means that the A/D converter can supply data in real-time without any interrupts and with no maximum number of samples for each acquisition. 22

Selecting an A/D Converter • First consideration is the connection between A/D converter and the computer. It should fit into one of the PC’s internal ports. • A/D converters fitting into the PC’s internal PCI port are commonly referred to as data acquisition boards (DABs). • Key features of a DAB are – Momory – Number of channels simultaneously sampled – Bandwidth – Range of input voltage 23

Analysis of Data • Spectrum Analysis: DAP samples with 8 bit amplitude resolution even though it would be sufficient to sample with only I bit. Sampling with 8 bits gives more detailed description of the input signal. The following figure shows the first 100 samples of the signal sampled with an amplitude resolution of 8 bits. 24

Acquisition Algorithms • Three algorithms may be described: – Serial search acquisition – Parallel frequency space search acquisition – Parallel code phase search acquisition. • Selection of data size for acquisition depends on: – Effect of navigation data bit transactions. – Probability of making a successful acquisition. – Calculational demands as a function of the length of data to be analyzed. 25

Serial Search Acquisition Incoming signal is multiplied with the locally generated PRN sequence. The 32 different PRN sequences are generated by the PRN generator which is implemented according to the figure in the next page. 26

PRN Code Generator using the Binary 0 and 1 27

Parallel Frequency Space Search Acquisition In the same way as with the serial search acquisition method, the implementation of the parallel frequency space search method is very straight-forwarded. 28

Parallel Code Phase Search Acquisition The best choice! 29

Selection of Acquisition Algorithms • One of the previous algorithms should be selected to be used in the receiver. • The selection should be based on execution time and parameter estimation. • Other properties such as flexibility and complexity should be taken into account also. • Regarding execution time, the parallel code phase search algorithm has a great advantage. • Regarding parameter estimation, all algorithms perform well. The parallel frequency space search has a draw back of its limit of 1 k. Hz frequency resolution. • One good thing about the serial search algorithm is that it is very flexible. With this algorithm, it is possible to select only some frequencies and only some code phases. 30

Code Tracking • In-phase Code Tracking: This tracking loop contains three code correlators. The tracking loop uses block processing to process the data. • Because of the sample frequency of about 11. 9988 MHz each frame of data is approximately 1 ms long. • First the signal is demodulated to baseband. This is done by multiplying the 11. 999 samples in the input frame with a local carrier replica. When the carrier has been wiped out, the tracking loop correlates the signal with three codes replicas or three crosscorrelators (early, prompt, and late). The outputs are shown in the following figure. 31

In-phase and Quadrature Code Tracking • If the code tracking loop performance has to be independent of the performance of the phase lock loop, the tracking loop has to use both the in-phase and quadrature arm to track the code. 32

References • Global Positioning Systems by MS Grewal, LR Weill, AP Andrews, Wiley, 2001. • Peter Rinder and Nicolaj Bertelsen, Design of a Single GPS Software Receiver, Aalborg University 2004. • Lecture notes of the instructor. • The Internet. 33