Delay Mechanisms transport reject timeexp inertial Transport Ideal

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Delay Mechanisms transport | [reject time_exp] inertial • Transport: Ideal transmission line • Inertial:

Delay Mechanisms transport | [reject time_exp] inertial • Transport: Ideal transmission line • Inertial: Model rejection of short pulses

Transport Delay entity transp_dly is end entity transp_dly ; --------------------------------architecture test of transp_dly is

Transport Delay entity transp_dly is end entity transp_dly ; --------------------------------architecture test of transp_dly is signal line_in, line_out : bit : = '0'; begin transmission_line : process (line_in) is begin line_out <= transport line_in after 500 ps; end process transmission_line; --------stimulus : process is begin line_in <= '1' after 2000 ps, '0' after 4000 ps, '1' after 6000 ps, '0' after 6200 ps, '1' after 8000 ps, '0' after 8200 ps, '1' after 8300 ps, '0' after 8400 ps; wait; end process stimulus; end architecture test;

Transport Delay entity transp_dly 1 is end entity transp_dly 1 ; architecture test of

Transport Delay entity transp_dly 1 is end entity transp_dly 1 ; architecture test of transp_dly 1 is signal a, z : bit; begin asym_delay : process (a) is constant Tpd_01 : time : = 800 ps; constant Tpd_10 : time : = 500 ps; begin if a = '1' then z <= transport a after Tpd_01; else -- a = '0‘ z <= transport a after Tpd_10; end if; end process asym_delay; stimulus : process is begin a <= '1' after 2000 '0' after 4000 '1' after 6000 '0' after 6200 wait; end process stimulus; end architecture test; ps, ps, ps;

Inertial Delay entity inertial_dly is end entity inertial_dly; --------------------------------architecture test of inertial_dly is signal

Inertial Delay entity inertial_dly is end entity inertial_dly; --------------------------------architecture test of inertial_dly is signal top_a, bottom_a : bit : = '0'; signal top_y, bottom_y : bit; begin inv_top : process (top_a) is begin top_y <= inertial not top_a after 3 ns; end process inv; --------stimulus_inertial_dly : process is begin top_a <= '1' after 1 ns, '0' after 6 ns, '1' after 8 ns; wait; end process stimulus_inertial_dly ; end architecture test;

Inertial Delay entity inertial_dly 1 is end entity inertial_dly 1; --------------------------------architecture test of inertial_dly

Inertial Delay entity inertial_dly 1 is end entity inertial_dly 1; --------------------------------architecture test of inertial_dly 1 is signal top_a, bottom_a : bit : = '0'; signal top_y, bottom_y : bit; begin inv_bottom : process (bottom_a ) is begin bottom_y <= reject 2 ns inertial not bottom_a after 3 ns; end process inv; --------stimulus_inertial_dly 1 : process is begin bottom_a <= '1' after 1 ns, '0' after 6 ns, '1' after 9 ns, '0' after 11. 5 ns, '1' after 16 ns, '0' after 18 ns, '1' after 19 ns, '0' after 20 ns; wait; end process stimulus_inertial_dly 1 ; end architecture test;

Conditional Signal Assignment • name <= [delay_mechanism] {waveform when bool_expr else} waveform [when bool_expr];

Conditional Signal Assignment • name <= [delay_mechanism] {waveform when bool_expr else} waveform [when bool_expr];

Conditional Signal Assignment zmux : z <= d 0 when sel 1 '0' else

Conditional Signal Assignment zmux : z <= d 0 when sel 1 '0' else d 1 when sel 1 '1' else d 2 when sel 1 '0' else d 3 when sel 1 '1'; = '0' and sel 0 = = '1' and sel 0 = zmux : process is begin if sel 1 = '0' and sel 0 = '0' then z <= d 0; elsif sel 1 = '0' and sel 0 = '1' then z <= d 1; elsif sel 1 = '1' and sel 0 = '0' then z <= d 2; elsif sel 1 = '1' and sel 0 = '1' then z <= d 3; end if; wait on d 0, d 1, d 2, d 3, sel 0, sel 1; end process zmux;

Selected Signal Assignment • with expr select name <= [delay_mechanism] {waveform when choices, }

Selected Signal Assignment • with expr select name <= [delay_mechanism] {waveform when choices, } waveform when choices;

Selected Signal Assignment alu : with alu_function select result <= a + b after

Selected Signal Assignment alu : with alu_function select result <= a + b after Tpd when alu_add | alu_add_unsigned, a - b after Tpd when alu_sub | alu_sub_unsigned, a and b after Tpd when alu_and, a or b after Tpd when alu_or, a after Tpd when alu_pass_a; alu : process is begin case alu_function is when alu_add | alu_add_unsigned => result <= a + b after Tpd; when alu_sub | alu_sub_unsigned => result <= a - b after Tpd; when alu_and => result <= a and b after Tpd; when alu_or => result <= a or b after Tpd; when alu_pass_a => result <= a after Tpd; end case; wait on alu_function, a, b; end process alu;