Delay Line Update 72803 Ian Harnarine Everything you

Delay Line Update 7/28/03 Ian Harnarine Everything you Ever Wanted to Know About Delay Lines & NICADD (but were afraid to ask) NICADD Weekly Meeting

Delay Line Update 7/28/03 Ian Harnarine • What is a delay line? It has various uses, but we’ll use it to ensure proper circuit timing. • Passive Delay Lines: Analog, composed of capacitors and inductors. • Active Delay Lines: Digital, use integrated circuits. Inputs and outputs interfaced for TTC, ECL & CMOS.

Delay Line Update 7/28/03 Ian Harnarine • Considerations when using Delay Lines: • Input rise time must be faster than the output rise time. • The maximum delay for a delay line must be smaller than the width of the pulse. • Taps? • Provide the many points along the device that one can adjust the timing incrementally along the delay line. • Merely connections between inductor/capacitor arrays.

Delay Line Update 7/28/03 Ian Harnarine • Our Requirements: • Smallest Rise Time as possible (10 -40 ns) • Total delay of 130 ns • For use with a ~20 -50 ns pulse that is 3 V • $$ CHEAP $$

Delay Line Update 7/28/03 Ian Harnarine • …. And the Winner is (drum roll, please): SIP 5 Series 10 -Tap HP Passive Delays: 2 x 45 ns + 1 x 40 ns = 130 ns R. T. =2 x 8. 2 ns + 7. 0 ns=23. 40 ns

Delay Line Update 7/28/03 Ian Harnarine • Schematic of 10 -Tap SIP 5: YES, THIS IS AN INDUCTOR 1 2 3 COM N/C IN 4 5 10% 20% 6 7 30% 40% 8 9 10 11 12 13 14 50% 60% 70% 80% 90% 100% COM

Delay Line Update 7/28/03 Ian Harnarine • Why not just ONE 130 ns delay line? • One unit would have a greater rise time than three combined units of smaller rise times • A unit with 30 ns rise time could cause signals <50 ns to be reduced to a saw-tooth pattern as the rising and falling edges collapsed towards the centre of the pulse.