Delay FPGA IO Clock 40 4 Clock 40

Delay FPGA I/O Clock 40 4 Clock 40 Reset delay_ser_out delay_ser_in busy ADC_Data_stream_0 5 ADC_Data_stream_0 10 Delay FPGA ADC_Data_stream_3 Multi function Non I/O pins 10 Configuration Bank Drive Voltages Core Voltage, gnd Rutherford Appleton Laboratory 1 1 1 Instrumentation Department 5 ADC_Data_stream_3 Bank DCI Resistors Bank Ref Voltages 2 TEMP SENSE - NF JTAG Electronic System Design Group Design I/O Total = 73+ XC 2 V 40 CS 144 - 88 I/O XC 2 V 80 FG 144 - 92 I/O Rob Halsall et al. 17 October 2001

Delay FPGA Function 4 phases XC 2 V 40 -CS 144 CLOCK OUT 0 CLOCK - 40 MHz DCM 0 IOB 5 Slices REG 10 1 REG DCI SHIFT REG REG DATA OUT 0 BLOCK RAM 0 10 Slices DPM Counter 2. 5/3. 3 V I/O? 4 phases CLOCK OUT 3 1. 5/1. 8/2. 5/3. 3 V I/O? DCM 3 IOB 5 Slices REG 10 4 10 REG DCI SHIFT REG DATA OUT 3 REG BLOCK RAM 3 10 Slices DPM Control Counter Clock RESET Serial In CONTROL Serial Out busy Rutherford Appleton Laboratory Instrumentation Department Electronic System Design Group Rob Halsall et al. 17 October 2001

CMS Tracker FED - Front End FPGA Floorplan Die Package FE-BE I/O ADC_Data Channel 0 Channel 3 Delay - Opto - ADC Clocks Rutherford Appleton Laboratory Instrumentation Department XC 2 V 40 CS 144 - 88 I/O XC 2 V 80 CS 144 - 92 I/O XC 2 V 250 CS 144 - 92 I/O Electronic System Design Group Rob Halsall et al. 17 October 2001