Datapath Elements in VHDL Will look at how

Datapath Elements in VHDL • Will look at how to implement some common datapath elements in VHDL – – – Register (reg 8. vhd) Counter (cnt 4. vhd) Comparator (cmp 8. vhd) Registered Comparator (cmp 8_reg. vhd) Muxes (mux 4 to 1_8_seq. vhd, mux 4 to 1_8_conc. vhd, muxbad. vhd) • Look at http: //www. erc. msstate. edu/~reese/EE 4743/vhdl for code listings BR 1/99 1

Comments on Code listings Counter has the header: library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_arith. all; use ieee. std_logic_unsigned. all; The std_logic_arith package declares common arithmetic functions for std_logic types. The std_logic_unsigned package causes these arithmetic functions to operate on unsigned numbers. The std_logic_signed package would operate on signed numbers (affects comparisons, multiplications). BR 1/99 2

Muxes Lots of different ways to do muxes in VHDL. The muxbad example uses if statements - this may not synthesize as well as using either the CASE or SELECT statements. For Altera, the synthesis results were: Mux (CASE statement - sequential) - 24 Logic Cells Mux (SELECT statement - concurrent) - 24 Logic Cells Mux (If-else statement) - 27 Logic cells With the CASE or SELECT statements, the synthesis can assume a mux structure. With the If-Else construct, a priority chain is first assumed, which may simply to a mux implementation based on the conditions being tested. BR 1/99 3

Registered Logic C O M B D F F S The easiest way to make blocks of logic with DFFs used for registering the outputs is shown in the cmp 8_reg. vhd example. Notice that the process does NOT have a sensitivity list and uses a ‘wait’ statement on the clock. BR 1/99 4