DAQ Hardware For LS 1 IIHEULB Gilles De

DAQ Hardware For LS 1 IIHE-ULB Gilles De Lentdecker Yifan Yang Erik Verhagen Michael Korntheuer Yifan Yang--- DAQ Hardware for LS 1 1

Overview • Off-detector electronics • • micro. TCA environment introduction Brussels activities • Opto Hybrid FPGA Board • • Challenges and possible solution Prototype board plan • Summary Yifan Yang--- DAQ Hardware for LS 1 2

Overview • Off-detector electronics • • micro. TCA environment introduction Brussels activities • Opto Hybrid FPGA Board • • Challenges and possible solution Prototype board plan • Summary Yifan Yang--- DAQ Hardware for LS 1 3

System overview GE 1/1 Superchamber GE 2/1 Reference plane 15 Column 5 FPGA boards 4 Glib 1 AMC 13 Port 8 -11 PCIe or customized protocol (GLIBs to AMC 13) AMC 13/GLIB Yifan Yang--- DAQ Hardware for LS 1 GLIB 4

Overview • Off-detector electronics • • micro. TCA environment introduction Brussels activities • Opto Hybrid FPGA Board • • Challenges and possible solution Prototype board plan • Summary Yifan Yang--- DAQ Hardware for LS 1 5

u. TCA developments • We already got : – 1 AMC 13 – 1 GLIB v 2 • We should get soon: – 6 GLIBs v 3 • In Brussels lab: 3 u. TCA crates (2 NAT & 1 Vadatech VT 892) Already built two AMC (w/o FPGA) A mezzanine with 2 FPGAs Already some experience with u. TCA world (MCH, MMC, IPMI, etc. ) – These developments are also valuable for LS 1 – – Yifan Yang--- DAQ Hardware for LS 1 6

Overview • Off-detector electronics • • micro. TCA environment introduction Brussels activities • Opto Hybrid FPGA Board • • Challenges and possible solution Prototype board plan • Summary Yifan Yang--- DAQ Hardware for LS 1 7

Opto Hybrid FPGA Board GEM chamber segmentation VFAT 2 1 2 3. . . Eta partitions A B Columns C Δϕ=10° μTCA Crate (12 slots) @3. 2 Gbps AMC 13 Glib To CSC system Glib Yifan Yang--- DAQ Hardware for LS 1 8

Space limitation Yifan Yang--- DAQ Hardware for LS 1 9

Large number of signals MOLC 200 4 ways-- potentially more layers are needed Panasonic 160 2 ways-- more signals needed to be shared and 24 VFAT 2 Yifan Yang--- DAQ Hardware for LS 1 10

Large number of signals • VFAT 2 from 30 to 24, S bits and Dataout differential signals decrease to 432 • MCLK, T 1, RSTb are shared by column instead of channel, decrease to 15 • I 2 C and DACO_V/I keep at 24 • 471 signals in total can be fit into 3 Panasonic 160 2 ways connectors. • By using SN 65 LVDS 386(16 channel LVDS receiver) , signals on FPGA can be reduced to 249. Yifan Yang--- DAQ Hardware for LS 1 11

High speed link • As GBT Emulator, 4. 8 Gbps transceiver is required. • GTX--- 6. 6 Gbps only in Virtex 6 • GTP--- 3. 2 Gbps in Virtex 5 and spartan 6 • By using Virtex 6, part of the CSC system firmware can be reused and also possible for emulating GBT link which benefit LS 2 design Yifan Yang--- DAQ Hardware for LS 1 12

Possible FPGA Embedded XADC is another advantage Yifan Yang--- DAQ Hardware for LS 1 13

Power and cooling • • 1. 5 V 4 A 3. 3 V 3 A 15. 9 W in total Cooling by attaching metal to air pipe Yifan Yang--- DAQ Hardware for LS 1 14

LHC clock and synchronization • Copper cable is the easiest way to get 40. 08 MHz LHC clock but too far away • TTC system has to be used • TTCrx+QPLL • Command decoder on opto hybrid • Fixed latency transfer to CSC and Glib Yifan Yang--- DAQ Hardware for LS 1 15

Radiation environment – Snap 12 Transmitter: < 1 SEU per year per link – Snap 12 Receiver: ~1 SEU per week per link • These typically just affect a single data word – Finisar Optical Transceiver: ~7 SEU/day/link • Typically just affects a single data word • Low rate, less than one error in 3 *1013 bits – FPGA GTX Transceivers: ~3 SEU/year/link – FPGA Block RAMs: ~9 SEU/day/chip • These typically affect a single bit in a single cell • Need to investigate mitigation for FPGA BRAMs – FPGA CLBs: ~6 SEU/day/chip • Need to investigate mitigation for FPGA CLBs Yifan Yang--- DAQ Hardware for LS 1 16

Firmware design Yifan Yang--- DAQ Hardware for LS 1 17

Firmware design • • • Trigger data readout Tracking data readout VFAT 2 control TTC system Slow control SEU control Yifan Yang--- DAQ Hardware for LS 1 18

Overview • Off-detector electronics • • micro. TCA environment introduction Brussels activities • Opto Hybrid FPGA Board • • Challenges and possible solution Prototype board plan • Summary Yifan Yang--- DAQ Hardware for LS 1 19

Prototype board plan Evaluate connector signal integrity and other component(TTCrx, QPLL) Estimate logic resource usage for full system and 3. 2 Gbps connection Try refreshing firmware and maybe other mitigation methods Yifan Yang--- DAQ Hardware for LS 1 20

Time estimate • Schematic design before April (away for two weeks in February ) from now 1. 5 month • PCB design before mid of May 1. 5 month • Assembling before June 0. 5 month • Firmware design • • • Reuse RPC design for TTC system 1. 5 month Reuse TOTEM design for VFTA 2 control 1 month Reuse CSC design for trigger data readout 1. 5 month Opto Hybrid board part Slow control and SEU control 1 month Integration of all function module 1 month • Trigger and tracking data receiver 1 month • Segment trigger algorithm implementation 2 month • Communication with AMC 13 1 month UTCA part • DAQ Software design Yifan Yang--- DAQ Hardware for LS 1 21

Overview • Off-detector electronics • • micro. TCA environment introduction Brussels activities • Opto Hybrid FPGA Board • • Challenges and possible solution Prototype board plan • Summary Yifan Yang--- DAQ Hardware for LS 1 22

summary • • Study is ongoing Prototype design is ongoing Communication is very important Suggestions are welcome Yifan Yang--- DAQ Hardware for LS 1 23

Thank you! Yifan Yang--- DAQ Hardware for LS 1 24

Backup Yifan Yang--- DAQ Hardware for LS 1 25

micro. TCA • Little brother of ATCA (Advanced Telecommunications Computing Architecture) – the largest specification effort in the history of the PCI Industrial Computer Manufacturers Group (PICMG) – Offers a flexible, high density, high performance backplane based on serial standards used today (Gb. E, PCIe, …) – Large effort in CMS to replace VME by micro. TCA for upgrades Yifan Yang--- DAQ Hardware for LS 1 26

AMC • Advanced Mezzanine Card (AMC) • micro. TCA is based on the AMC standard initially developed for the ATCA cards. • Up to 12 AMC cards can be inserted into the micro. TCA backplane • The MCH (Micro. TCA Carrier Hub) provides the connectivity between slots – Provides also crate management functions • The system can operate in redundant mode with a second MCH Yifan Yang--- DAQ Hardware for LS 1 27

GLIB (see S. Haas talk https: //indico. cern. ch/conference. Display. py? conf. Id=182546) • An evaluation AMC card for bench-top operation or use in a u. TCA crate • Expandable via FMC, two mezzanine slots AMC features: Mid-size double-width AMC 4 SFP+ transceiver modules Virtex-6 FPGA with twenty 6. 5 Gbps transceivers I/O capability can be further enhanced with 2 FPGA Mezzanines Gigabit Ethernet link to PC for bench-top operation To u. TCA backplane 4 SFP+ Yifan Yang--- DAQ Hardware for LS 1 28

AMC 13 (see E. Hazen talk https: //indico. cern. ch/conference. Display. py? conf. Id=182546) • It is not an MCH! It is a 13 th AMC in MCH-2 slot (as permitted by Micro. TCA standard) • It distributes LHC clock / timing / controls to AMCs • It collects DAQ data from AMCs • It provides standard interface to CMS subdetectors: – CMS DAQ via optical fibers (currently 2 at ~ 5 Gb/s) – TTC via 1300 nm fiber @ 160 Mb/sec biphase mark code • Future TTC upgrade may be supported via spare SFP site – TTS via 1300 nm fiber with protocol t. b. d. Yifan Yang--- DAQ Hardware for LS 1 29

AMC 13 (HCAL example) Yifan Yang--- DAQ Hardware for LS 1 30