D Latches and FlipFlops ECE 352 Digital System

D Latches and Flip-Flops ECE 352 Digital System Fundamentals D Latches and Flip-Flops 1

D Latches and Flip-Flops Storage Elements • Many interesting types of circuits require keeping track of what happened in the past • Need to store some of this past information • • 2 • Generally not storing everything that happened, just some key information Example: Vending machine • • Needs to track how much money was inserted Doesn’t need to track which coins/bills were used How can we store this data?

What Does This Do? D Latches and Flip-Flops • Once we can get a value into this structure, it stays there as long as the circuit has power Can hold a 1 Can hold a 0 1 0 0 1 How do we get a value into this structure in the first place? 3

D Latch with Control D Latches and Flip-Flops • 4 • • Want to control what goes into the storage element and when it happens The bottom inverter is weak, and the tristate can overpower it without damage This latch is level-sensitive: the value held in the latch can change whenever signal C is 1 Symbol

D Latches and Flip-Flops Level-Sensitivity Problem • Consider a counter built with latches: • Stored value could update many times while C=1 • 5 • • The number of times it updates is unpredictable! Update rate also depends on ambient temperature… We want to update once per pulse on signal C • We want deterministic behavior!

D Latches and Flip-Flops Clock Signal 6 • Need ability to make circuits where the storage elements only change at a pre-determined rate • A clock is a special signal that oscillates between value of 1 and 0 at a specific frequency • Controls how often the storage elements can update (“positive” edge) (“negative” edge)

D Flip-Flop D Latches and Flip-Flops • • Build a “flip-flop” (FF) by connecting two latches so the first latch’s output is the second’s input The output of the below flip-flop only changes on the negative edge of the control signal (the clock) Flip-Flop 1 st Latch 2 nd Latch Symbol “bubble” means negative-edge! 7

Flip-Flop Waveform D Latches and Flip-Flops • 8 The waveform demonstrates how the two latches work together to act as an edge-triggered FF • Colors on the waveform indicate which latch is enabled FF output Q changes on negative clock edge The first latch is only enabled when the second cannot change. The second latch is only enabled when the first cannot change.

Positive-Edge Triggering D Latches and Flip-Flops • A positive-edge triggered flip-flop can be constructed by adding an inverter • This changes which latch is enabled for the high vs. low phase of the clock Symbol “no bubble” means positive-edge! 9

Flip-Flops and Timing Waveforms D Latches and Flip-Flops • 10 In reality, there is some delay after the active clock edge before the FF input is stored and appears at the FF output

Flip-Flops and Functional Waveforms D Latches and Flip-Flops • The functional waveform does not show delay, but it still expresses causality • The value of a FF’s output just after the active clock edge is the value of its input just before that clock edge B’s changes do not show up at Y until the next clock edge! 11

Flip-Flop Direct Inputs D Latches and Flip-Flops • Sometimes we need a FF to hold a specific value immediately (before the next active clock edge) • • • Commonly used to force a circuit’s flip-flops into a known desired state on start-up • • 12 An asynchronous input affects the flip-flop immediately, without requiring an active clock edge A synchronous input has no effect unless the clock is at an active edge Direct set (preset) forces flip-flop to 1 Direct reset (clear) forces flip-flop to 0 Symbol

Flip-Flops Direct Inputs In Quartus D Latches and Flip-Flops • 13 • The flip-flops available in Quartus have activelow preset (PRN) and clear (CLRN) inputs • • PRN = 0 forces the FF to immediately store a 1 CLRN = 0 forces the FF to immediately store a 0 You need to tie these inputs to 1 (VCC) to disable them if you are not using them! Do NOT leave them unconnected! D flip-flop with reset and disabled preset

D Latches and Flip-Flops ECE 352 Digital System Fundamentals D Latches and Flip-Flops 14

D Latches and Flip-Flops Questions 15 A. A latch is ____-sensitive. B. A flip-flop is ____-sensitive. C. The output of a negative-edge triggered flip-flop only changes when ____. D. The output of a positive-edge triggered flip-flop only changes when ____. E. When an asynchronous preset input is active, it forces the flip-flop to ____. F. When an asynchronous clear input is active, it forces the flip-flop to ____.