Cypress Roadmap Platform PSo C Q 1 2015

Cypress Roadmap: Platform PSo. C® Q 1 2015 001 -89679 Rev *F Owner: JFMD BUM: GOPA Platform PSo. C Roadmap

PSo. C® 1 Portfolio M 8 C Core | 24 MHz PSo. C MCU Programmable Digital Intelligent Analog Performance Analog CY 8 C 29 xxx 32 K/2 K 1, 64 GPIOs 2 Cap. Sense, 16 x Prog. Digital Blocks 3 4 x CMP 4, 1 x 14 -bit ΔƩ ADC 5, 12 x SC/CT PAB 6 CY 8 C 27 xxx 32 K/2 K 1, 44 GPIOs 2 Cap. Sense, 8 x Prog. Digital Blocks 3 4 x CMP 4, 1 x 14 -bit ΔƩ ADC 5, 12 x SC/CT PAB 6 CY 8 C 24 x 94 16 K/1 K 1, 56 GPIOs 2 Cap. Sense, 4 x Prog. Digital Blocks 3 2 x CMP 4, 2 x 14 -bit SAR ADC 5, 6 x SC/CT PAB 6 CY 8 C 28 xxx 16 K/1 K 1, 44 GPIOs 2 Cap. Sense, 12 x Prog. Digital Blocks 3 4 x CMP 4, 4 x 14 -bit ΔƩ ADC 5, 16 x SC/CT PAB 6 Performance CY 8 C 2 xx 45 16 K/1 K 1, 38 GPIOs 2 Cap. Sense, 8 x Prog. Digital Blocks 3 4 x CMP 4, 1 x 10 -bit SAR ADC 5, 6 x SC/CT PAB 6 CY 8 C 21 x 34 8 K/0. 5 K 1 , 28 GPIOs 2 Cap. Sense, 4 x Prog. Digital Blocks 3 2 x CMP 4, 1 x 10 -bit ADC 5, 4 x SC/CT PAB 6 CY 8 C 24 x 23 4 K/0. 25 K 1, 24 GPIOs 2 Cap. Sense, 4 x Prog. Digital Blocks 3 2 x CMP 4, 1 x 14 -bit ΔƩ ADC 5, 6 x SC/CT PAB 6 CY 8 C 23 x 33 8 K/0. 25 K 1, 26 GPIOs 2 Cap. Sense, 4 x Prog. Digital Blocks 3 1 x CMP 4, 1 x 8 -bit SAR ADC 5, 4 x SC/CT PAB 6 CY 8 C 21 x 23 4 K/0. 25 K 1, 16 GPIOs 2 4 x Prog. Digital Blocks 3 2 x CMP 4, 1 x 10 -bit ADC 5, 4 x SC/CT PAB 6 CY 8 C 24 x 93 32 K/2 K 1, 36 GPIOs 2 2 x CMP 4, 1 x 10 -bit ADC 5 Flash KB/SRAM KB input output pins 3 Programmable digital block Comparator 1 4 2 General-purpose 5 Analog-to-digital 001 -89679 Rev *F Integration converter (incremental, successive approximation (SAR) or Delta-Sigma ( ΔƩ)) Status 6 Switched capacitor/continuous time programmable analog block Availability Owner: JFMD Platform PSo. C Roadmap BUM: GOPA Production Sampling Development Concept QQYY

PSo. C® 3 Portfolio 8051 | Cap. Sense® | DMA | LCD | RTC | 4 x Timer/Counter/PWM Programmable Digital PSo. C 3200 Intelligent Analog PSo. C 3400 Performance Analog PSo. C 3600 Precision Analog PSo. C 3800 Analog: ΔƩ ADC 1, 1 x DAC 2, 2 x CMP 3, 0. 9% Vref Analog: ΔƩ ADC 1, 2 x DAC 2, 4 x CMP 3, 2 x Opamps, 2 x SC/CT PAB 5, 0. 9% Vref Interfaces: FF 4 I 2 C Analog: ΔƩ ADC 1, 2 x/4 x DAC 2, 0 x/2 x/4 x CMP 3, 0 x/2 x/4 x Opamps, 0 x/2 x/4 x SC/CT PAB 5, 0. 1% Vref Interfaces: USB, FF 4 I 2 C CY 8 C 3666 67 MHz, 64 K/8 K/2 K 6 0 x/1 x DFB 5, 12 b ADC 1 20 x/24 x UDB 6, CAN 9 Performance NEW NEW CY 8 C 3246 50 MHz, 64 K/8 K/2 K 6 12 b ADC 1 24 x UDB 8, USB, 72 -CSP 10 CY 8 C 3446 50 MHz, 64 K/8 K/2 K 6 12 b ADC 1 24 x UDB 8, USB, CAN 9 CY 8 C 3245 50 MHz, 32 K/4 K/1 K 6 12 b ADC 1 20 x UDB 8, USB, 72 -CSP 10 CY 8 C 3445 50 MHz, 32 K/4 K/1 K 10 12 b ADC 1 20 x UDB 8, USB CY 8 C 3244 50 MHz, 16 K/2 K/0. 5 K 6 12 b ADC 1 16 x UDB 8 CY 8 C 3444 50 MHz, 16 K/2 K/0. 5 K 6 12 b ADC 1 16 x UDB 8 CY 8 C 3665 67 MHz, 32 K/4 -8 K/1 K 6 0 x/1 x DFB 7, 12 b ADC 1 16 x/20 x UDB 8, 72 -CSP 10 Integration Delta-Sigma analog-to-digital converter 2 Digital-to-analog converter 3 Comparator 001 -89679 Owner: JFMD Rev *F BUM: GOPA 1 Fixed function 5 Switched capacitor/continuous time programmable analog block 4 Flash KB/SRAM KB/EEPROM KB 5 Digital filter block 6 Universal digital block Platform PSo. C Roadmap 6 9 NEW CY 8 C 3866 67 MHz, 64 K/8 K/2 K 6 DFB 7, 20 b ADC 1 20 x/24 x UDB 8, CAN 9, 72 -CSP 10 CY 8 C 3865 67 MHz, 32 K/4 -8 K/1 K 6 0 x/1 x DFB 7, 20 b ADC 1 16 x/20 x UDB 8 Production Sampling Development Concept Controller area network Status Chip scale package 10 QQYY Availability 10

PSo. C® 4 Portfolio ARM® Cortex™-M 0 | Cap. Sense® PSo. C MCU PSo. C 4000 Intelligent Analog PSo. C 4100 BL = BLE-Series M = M-Series Q 215 CY 8 C 4127 -M 24 MHz, 128 K/16 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6, CAN 9 Performance NEW Q 215 CY 8 C 4127 -BL 24 MHz, 128 K/16 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6, BLE 7 Q 315 Q 215 NEW Q 315 NEW CY 8 C 4247 -L CY 8 C 4247 -M CY 8 C 4247 -BL 48 MHz, 128 K/16 K 1, CMP 2, 2, Opamp, ADC 3, SCB 4, CMP Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6, UDB 8, CAN 9 TCPWM 6, BLE 7, UDB 8 USB CY 8 C 4246 -L CY 8 C 4246 -M 48 MHz, 64 K/8 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6, UDB 8, CAN 9, 5 6 8 IDAC , TCPWM , UDB USB CY 8 C 44 x 6 48 MHz, 64 K/16 K 1 Concept Only Contact Sales CY 8 C 4125 24 MHz, 32 K/4 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6 CY 8 C 4245 48 MHz, 32 K/4 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6, UDB 8 CY 8 C 44 x 5 48 MHz, 32 K/8 K 1 Concept Only Contact Sales CY 8 C 4124 24 MHz, 16 K/4 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6 CY 8 C 4244 48 MHz, 16 K/4 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6, UDB 8 CY 8 C 4126 -M 24 MHz, 64 K/8 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6 CY 8 C 4014 16 MHz, 16 K/2 K 1, CMP 2, I 2 C, IDAC 5, TCPWM 6 NEW L = L-Series NEW CY 8 C 4248 -L CY 8 C 4248 -BL 48 MHz, 256 K/32 K 1, CMP 2, 2 3 4 CMP , Opamp, ADC , SCB , Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6, UDB 8, CAN 9, TCPWM 6, BLE 7, UDB 8 USB CY 8 C 4128 -BL 24 MHz, 256 K/32 K 1, CMP 2, Opamp, ADC 3, SCB 4, IDAC 5, TCPWM 6, BLE 7 NEW Programmable Analog PSo. C 4400 Programmable Digital PSo. C 4200 CY 8 C 4013 16 MHz, 8 K/2 K 1, IDAC 5, TCPWM 6 CMP 2, I 2 C, Integration 1 Flash 4 Serial communication block programmable as I 2 C/SPI/UART 7 Bluetooth Low Energy KB/SRAM KB 2 Comparator 5 Current-output digital-to-analog converter 8 Universal Digital Block 3 Analog-to-digital converter 6 Timer, counter, PWM block 9 Controller Area Network 001 -89679 Owner: JFMD Platform PSo. C Roadmap Rev *F BUM: GOPA Production Sampling Development Concept Status Availability QQYY

PSo. C® 4000 PSo. C MCU Family Applications Block Diagram MCU and discrete analog replacement User interface for button replacement User interface for heating, ventilation, air conditioning PSo. C 4 One-Chip Solution MCU Subsystem Programmable Analog Blocks I/O Subsystem GPIO x 8 CORTEX-M 0 32 -bit MCU subsystem 16 -MHz ARM® Cortex™-M 0 CPU Up to 16 KB flash and 2 KB SRAM Programmable analog Two IDACs 1 (7 -bit and 8 -bit), digitally controlled current source One comparator (CMP) Cap. Sense® with Smart. Sense™ Auto-tuning One Cypress Capacitive Sigma-Delta™ (CSD) controller Capacitive sensing supported on up to 16 pins Programmable digital One configurable 16 -bit timer, counter or pulse-width modulator (TCPWM) block One I 2 C master or slave Packages 8 -pin SOIC, 16 -QFN, 24 -pin QFN 1 16 MHz Flash (8 KB to 16 KB) SRAM (2 KB) Programmable Digital Blocks TCPWM I 2 C GPIO x 8 GPIO x 4 Availability Datasheet: PSo. C 4000 Technical Reference Manual: PSo. C 4000 Sampling: Production: Current-output digital-to-analog converter Owner: JFMD BUM: GOPA CSD Serial Wire Debug Collateral 001 -89679 Rev *F CMP Programmable Interconnect and Routing Features Advanced High-Performance Bus (AHB) IDAC 1 x 2 Platform PSo. C Roadmap Now

PSo. C® 4100 Intelligent Analog Family Applications Block Diagram User interface for home appliances Digital and analog sensor hub MCU and discrete analog replacement PSo. C 4 One-Chip Solution MCU Subsystem Programmable Analog Blocks Features 32 -bit MCU Subsystem 24 -MHz ARM® Cortex™-M 0 CPU Up to 32 KB flash and 4 KB SRAM Opamp x 2 SAR 1 ADC CMP x 2 CSD 8 -bit IDAC 2 7 -bit IDAC 2 GPIO x 8 Smart. Sense™ Auto-tuning Cypress Capacitive Sigma-Delta™ (CSD) controller Cap. Sense supported on up to 36 pins Programmable Analog Blocks Two comparators (CMPs) Two opamps, programmed as PGAs, CMPs, filters, etc. One 12 -bit, 1 -Msps SAR 1 ADC Two IDACs 2 (2 x 8 -bit, 2 x 7 -bit) Programmable Digital Blocks Four programmable 16 -bit TCPWM 3 blocks Two SCBs 4: I 2 C master or slave, SPI master or slave, or UART Packages: 28 -pin SSOP, 40 -pin QFN, 44 -pin TQFP, 48 -pin LQFP Flash (16 KB to 32 KB) SRAM (4 KB) Programmable Digital Blocks TCPWM 3 x 4 Serial Wire Debug Collateral 1 Successive 3 2 Current-output 4 GPIO x 8 SCB 4 x 2 GPIO x 4 Segment LCD Drive Datasheet: PSo. C 4 (CY 8 C 4100) Technical Reference Manual: PSo. C 4 Programmable Interconnect and Routing 24 MHz Advanced High-Performance Bus (AHB) CORTEX-M 0 Cap. Sense® with approximation register digital-to-analog converter 001 -89679 Owner: JFMD Rev *F BUM: GOPA I/O Subsystem Availability Sampling: Production: Timer, counter, PWM block Serial communication block programmable as I 2 C/SPI/UART Platform PSo. C Roadmap Now

PSo. C® 4200 Programmable Digital Family Applications Block Diagram User interface for home appliances Digital and analog sensor hub MCU and discrete analog replacement PSo. C 4 One-Chip Solution MCU Subsystem Programmable Analog Blocks Features 32 -bit MCU Subsystem 48 -MHz ARM® Cortex™-M 0 CPU Up to 32 KB flash and 4 KB SRAM SAR 1 ADC CMP x 2 CSD 8 -bit IDAC 2 7 -bit IDAC 2 GPIO x 8 Smart. Sense™ Auto-tuning Cypress Capacitive Sigma-Delta™ (CSD) controller Cap. Sense supported on up to 36 pins Programmable Analog Blocks Two comparators (CMPs) Two opamps, programmed as PGAs, CMPs, filters, etc. One 12 -bit, 1 -Msps SAR 1 ADC Two IDACs 2 (2 x 8 -bit, 2 x 7 -bit) Programmable Digital Blocks Four Universal Digital Blocks (UDBs): custom digital peripherals Four programmable 16 -bit TCPWM 3 blocks Two SCBs 4: I 2 C master or slave, SPI master or slave, or UART Flash (16 KB to 32 KB) SRAM (4 KB) 3 2 Current-output 4 TCPWM 3 x 4 Serial Wire Debug GPIO x 8 GPIO x 4 Segment LCD Drive Collateral 1 Successive UDB x 4 GPIO x 8 SCB 4 x 2 Packages: 28 -pin SSOP, 40 -pin QFN, 44 -pin TQFP, 48 -pin LQFP Datasheet: PSo. C 4 (CY 8 C 4200) Technical Reference Manual: PSo. C 4 Programmable Digital Blocks Programmable Interconnect and Routing 48 MHz Advanced High-Performance Bus (AHB) CORTEX-M 0 Cap. Sense® with approximation register digital-to-analog converter 001 -89679 Owner: JFMD Rev *F BUM: GOPA Opamp x 2 I/O Subsystem Availability Sampling: Production: Timer, counter, PWM block Serial communication block programmable as I 2 C/SPI/UART Platform PSo. C Roadmap Now

PSo. C® 4100 BLE-Series Intelligent Analog Family with Bluetooth Low Energy Block Diagram Features 32 -bit MCU subsystem 24 -MHz ARM® Cortex™-M 0 CPU Up to 256 KB flash and 32 KB SRAM Programmable AFE 1 Four opamps, configurable as PGAs, comparators, filters, etc. One 12 -bit, 1 -Msps SAR 2 ADC Cap. Sense® with Smart. Sense™ Auto-tuning One Cypress Capacitive Sigma-Delta™ (CSD) controller with touchpad capability Programmable digital logic Four configurable TCPWM 3 blocks: 16 -bit timer, counter or PWM Two configurable serial communication blocks (SCBs 4): I 2 C master or slave, SPI master or slave, or UART Packages 56 -pin QFN, 68 -pin CSP Bluetooth Smart connectivity with Bluetooth 4. 1 2. 4 -GHz BLE radio with integrated Balun PSo. C 4 BLE One-Chip Solution MCU Subsystem 24 MHz BLE System Flash (128 KB to 256 KB) SRAM (16 KB to 32 KB) Serial Wire Debug Datasheet: PSo. C 4 BLE (CY 8 C 4 XX 7 BLE) Sampling: Production: front end(s) approximation register 001 -89679 Owner: JFMD Rev *F BUM: GOPA 3 4 CMP x 2 I/O Subsystem GPIO x 8 SAR 2 ADC CSD Programmable Digital Blocks TCPWM 3 x 4 SCB 4 x 2 GPIO x 8 Segment LCD Drive GPIO x 4 Availability 2 Successive Opamp x 4 CORTEX-M 0 Collateral 1 Analog Programmable Analog Blocks Programmable Interconnect and Routing Sports and fitness monitors, wearable electronics, medical devices, home automation solutions, game controllers, sensor-based low-power systems for the Internet of Things (Io. T) Advanced High-Performance Bus (AHB) Applications Timer, counter, PWM block Serial communication block programmable as I 2 C/SPI/UART Platform PSo. C Roadmap Now 128 KB Now, 256 KB Q 2 2015

PSo. C® 4200 BLE-Series Programmable Digital Family with Bluetooth Low Energy Block Diagram Features 32 -bit MCU subsystem 48 -MHz ARM® Cortex™-M 0 CPU Up to 256 KB flash and 32 KB SRAM Programmable AFE 1 Four opamps, configurable as PGAs, comparators, filters, etc. One 12 -bit, 1 -Msps SAR 2 ADC Cap. Sense® with Smart. Sense™ Auto-tuning One Cypress Capacitive Sigma-Delta™ (CSD) controller with touchpad capability Programmable digital logic Four Universal Digital Blocks (UDBs): custom digital peripherals Four configurable TCPWM 3 blocks: 16 -bit timer, counter or PWM Two configurable serial communication blocks (SCBs 4): I 2 C master or slave, SPI master or slave, or UART Packages 56 -pin QFN, 68 -pin CSP Bluetooth Smart connectivity with Bluetooth 4. 1 2. 4 -GHz BLE radio with integrated Balun PSo. C 4 BLE One-Chip Solution MCU Subsystem 48 MHz BLE System Flash (128 KB to 256 KB) SRAM (16 KB to 32 KB) 4 ADC CSD Programmable Digital Blocks UDB x 4 TCPWM 3 x 4 SCB 4 x 2 GPIO x 8 GPIO x 4 Sampling: Production: 3 GPIO x 8 SAR 2 Segment LCD Drive Datasheet: PSo. C 4 BLE (CY 8 C 4 XX 7 BLE) front end(s) approximation register 001 -89679 Owner: JFMD Rev *F BUM: GOPA CMP x 2 I/O Subsystem Serial Wire Debug Availability 2 Successive Opamp x 4 CORTEX-M 0 Collateral 1 Analog Programmable Analog Blocks Programmable Interconnect and Routing Sports and fitness monitors, wearable electronics, medical devices, home automation solutions, game controllers, sensor-based low-power systems for the Internet of Things (Io. T) Advanced High-Performance Bus (AHB) Applications Timer, counter, PWM block Serial communication block programmable as I 2 C/SPI/UART Platform PSo. C Roadmap Now 128 KB Now, 256 KB Q 2 2015

PSo. C® 4100 M-Series Intelligent Analog Family Block Diagram User interface and host processor for home appliances Digital and analog sensor hub MCU and discrete analog replacement PSo. C® 4 One-Chip Solution MCU Subsystem Programmable Analog Blocks Opamp x 4 Features Datasheet: GPIO x 8 24 MHz Flash (64 KB to 128 KB) SRAM (8 KB to 16 KB) Serial Wire Debug CAN x 2 CMP x 6 CSD 8 -bit IDAC 3 x 2 7 -bit IDAC 3 x 2 Programmable Digital Blocks TCPWM 4 x 8 PSo. C 4100 M datasheet 1 Real-time 3 2 Successive clock approximation register 001 -89679 Owner: JFMD Rev *F BUM: GOPA 4 GPIO x 8 SCB 5 x 4 GPIO x 8 Segment LCD Drive GPIO x 7 RTC 1 DMA Availability Collateral GPIO x 8 SAR 2 ADC Cortex-M 0 Advanced High-Performance Bus (AHB) 32 -bit MCU Subsystem 24 -MHz ARM® Cortex®-M 0 CPU with a DMA controller and RTC 1 Up to 128 KB flash and 16 KB SRAM Up to 55 GPIOs supporting analog, digital and Cap. Sense interfaces Cap. Sense® With Smart. Sense™ Auto-tuning Cypress Capacitive Sigma-Delta™ (CSD) controller Programmable Analog Blocks Six comparators (CMP) Four opamps, programmable as PGAs, CMPs, filters, etc. One 12 -bit, 1 -Msps SAR 2 ADC Four IDACs 3 (2 x 8 -bit, 2 x 7 -bit) Programmable Digital Blocks Eight programmable 16 -bit TCPWM 4 blocks Four SCBs 5: I 2 C master or slave, SPI master or slave, or UART Two Controller Area Network (CAN) Controllers Packages: 48 -pin LQFP, 64 -pin TQFP (0. 8 -mm pitch), 64 -pin TQFP (0. 5 -mm pitch), 68 -pin QFN I/O Subsystem Programmable Interconnect and Routing Applications Sampling: Production: Now Q 2 2015 Current-output digital-to-analog converter 5 Serial communication block programmable as I 2 C/SPI/UART Timer, counter, PWM block Platform PSo. C Roadmap

PSo. C® 4200 M-Series Programmable Digital Family Block Diagram User interface and host processor for home appliances Digital and analog sensor hub LED control and communication for lighting systems PSo. C® 4 One-Chip Solution MCU Subsystem Programmable Analog Blocks Opamp x 4 Features Datasheet: GPIO x 8 48 MHz Flash (64 KB to 128 KB) SRAM (8 KB to 16 KB) Serial Wire Debug CAN x 2 CMP x 6 CSD 8 -bit IDAC 3 x 2 7 -bit IDAC 3 x 2 Programmable Digital Blocks UDB x 4 TCPWM 4 x 8 PSo. C 4200 M datasheet 1 Real-time 3 2 Successive clock approximation register 001 -89679 Owner: JFMD Rev *F BUM: GOPA 4 GPIO x 8 RTC 1 SCB 5 DMA x 4 Segment LCD Drive Availability Collateral GPIO x 8 SAR 2 ADC Cortex-M 0 Advanced High-Performance Bus (AHB) 32 -bit MCU Subsystem 48 -MHz ARM® Cortex®-M 0 CPU with a DMA controller and RTC 1 Up to 128 KB flash and 16 KB SRAM Up to 55 GPIOs supporting analog, digital and Cap. Sense interfaces Cap. Sense® With Smart. Sense™ Auto-tuning Cypress Capacitive Sigma-Delta™ (CSD) controller Programmable Analog Blocks Six comparators (CMPs) Four opamps, programmable as PGAs, CMPs, filters, etc. One 12 -bit, 1 -Msps SAR 2 ADC Four IDACs 3 (2 x 8 -bit, 2 x 7 -bit) Programmable Digital Blocks Four Universal Digital Blocks (UDBs): custom digital peripherals Eight programmable 16 -bit TCPWM 3 blocks Four SCBs 4: I 2 C master or slave, SPI master or slave, or UART Two Controller Area Network (CAN) Controllers Packages: 48 -pin LQFP, 64 -pin TQFP (0. 8 -mm pitch), 64 -pin TQFP (0. 5 -mm pitch), 68 -pin QFN I/O Subsystem Programmable Interconnect and Routing Applications Sampling: Production: Now Q 2 2015 Current-output digital-to-analog converter 5 Serial communication block programmable as I 2 C/SPI/UART Timer, counter, PWM block Platform PSo. C Roadmap GPIO x 7

PSo. C® 4200 L-Series Programmable Digital Family Block Diagram User interface and host processor for home appliances Digital and analog sensor hub MCU and discrete analog replacement LED control and communication for lighting systems PSo. C® 4 One-Chip Solution MCU Subsystem Programmable Analog Blocks Features CSD x 2 8 -bit IDAC 3 x 2 7 -bit IDAC 3 x 2 Contact Sales 1 Real-time 3 2 Successive clock approximation register 001 -89679 Owner: JFMD Rev *F BUM: GOPA 4 GPIO x 8 ADC 48 MHz Flash (64 KB to 256 KB) SRAM (8 KB to 32 KB) Serial Wire Debug CAN x 2 Full-Speed USB 2. 0 GPIO x 8 Programmable Digital Blocks UDB x 8 TCPWM 4 x 8 RTC 1 DMA Sampling: Production: GPIO x 8 GPIO x 8 SCB 5 x 4 Segment LCD Drive Availability Collateral Preliminary Datasheet: CMP x 6 GPIO x 8 Cortex-M 0 Advanced High-Performance Bus (AHB) 32 -bit MCU Subsystem 48 -MHz ARM® Cortex® -M 0 CPU with a DMA controller and RTC 1 Up to 256 KB flash and 32 KB SRAM Up to 98 GPIOs supporting analog and digital interfaces Cap. Sense® With Smart. Sense™ Auto-tuning Two Cypress Capacitive Sigma-Delta™ (CSD) controllers Programmable Analog Blocks Two comparators (CMPs) Four opamps, configurable as PGAs, CMPs, filters, etc. One 12 -bit, 1 -Msps SAR 2 ADC Four IDACs 3 (2 x 8 -bit, 2 x 7 -bit) Programmable Digital Blocks Eight Universal Digital Blocks (UDBs): custom digital peripherals Eight configurable 16 -bit TCPWM 4 blocks Four SCBs 5: I 2 C master or slave, SPI master or slave, or UART Full-Speed USB 2. 0 Controller and Transceiver Two Controller Area Network (CAN) Controllers Packages: 48 -pin TQFP, 64 -pin TQFP, 68 -pin QFN, 124 -pin µBGA Opamp x 4 SAR 2 I/O Subsystem Programmable Interconnect and Routing Applications Q 3 2015 Q 4 2015 Current-output digital-to-analog converter 5 Serial communication block programmable as I 2 C/SPI/UART Timer, counter, PWM block Platform PSo. C Roadmap GPIO x 8 GPIO x 4

PSo. C® 5 LP Portfolio ARM® Cortex™-M 3 | Cap. Sense® | DMA | LCD | RTC | 4 x Timer/Counter/PWM Programmable Digital PSo. C 5200 Intelligent Analog PSo. C 5400 Performance Analog PSo. C 5600 Precision Analog PSo. C 5800 Analog: 1 x ADC 1, 1 x DAC 2, 2 x CMP 3, 0. 9% Vref Analog: 1 x ADC 1, 2 x DAC 2, 4 x CMP 3, 2 x Opamps, 2 x SC/CT PAB 5, 0. 9% Vref Interfaces: USB, FF 4 I 2 C Analog: 2 x ADC 1, 4 x DAC 2, 4 x CMP 3, 4 x Opamps, DFB 6, 4 x SC/CT PAB 5, 0. 9% Vref Interfaces: USB, FF 4 I 2 C, CAN 7 Analog: 2 x/3 x ADC 1, 4 x DAC 2, 4 x CMP 3, 4 x Opamps, DFB 6, 4 x SC/CT PAB 5, 0. 1% Vref Interfaces: USB, FF 4 I 2 C, CAN 7 Performance NEW CY 8 C 5288 80 MHz, 256 K/64 K/2 K 8 12 b SAR ADC 1 24 x UDB 9, 99 -CSP 10 NEW CY 8 C 5488 80 MHz, 256 K/64 K/2 K 8 12 b SAR ADC 1 24 x UDB 9, 99 -CSP 10 NEW CY 8 C 5688 80 MHz, 256 K/64 K/2 K 8 2 x 12 b SAR ADC 1 24 x UDB 9, 99 -CSP 10 CY 8 C 5268 67 MHz, 256 K/64 K/2 K 8 12 b SAR ADC 1 24 x UDB 9 CY 8 C 5468 67 MHz, 256 K/64 K/2 K 8 12 b SAR ADC 1 24 x UDB 9 CY 8 C 5668 67 MHz, 256 K/64 K/2 K 8 12 b ΔƩ ADC 11, 12 b SAR/2 x 12 b SAR ADC 1 24 x UDB 9 CY 8 C 5868 67 MHz, 256 K/64 K/2 K 8 20 b ΔƩ ADC 10, 2 x 12 b SAR ADC 1 24 x UDB 9 CY 8 C 5267 67 MHz, 128 K/32 K/2 K 8 12 b SAR ADC 1 24 x UDB 9 CY 8 C 5467 67 MHz, 128 K/32 K/2 K 8 12 b SAR ADC 1 24 x UDB 9 CY 8 C 5667 67 MHz, 128 K/32 K/2 K 8 12 b ΔƩ ADC 11, 12 b SAR/2 x 12 b SAR ADC 1 24 x UDB 9 CY 8 C 5867 67 MHz, 128 K/32 K/2 K 8 20 b ΔƩ ADC 11, 12 b SAR ADC 1 24 x UDB 9 CY 8 C 5266 67 MHz, 64 K/16 K/2 K 9 12 b SAR ADC 1 20 x UDB 10 CY 8 C 5466 67 MHz, 64 K/16 K/2 K 8 12 b SAR ADC 1 20 x UDB 9 CY 8 C 5666 67 MHz, 64 K/16 K/2 K 8 12 b ΔƩ ADC 11, 12 b SAR ADC 1 20 x UDB 9 CY 8 C 5866 67 MHz, 64 K/16 K/2 K 8 20 b ΔƩ ADC 11, 12 b SAR ADC 1 20 x UDB 9 CY 8 C 5265 67 MHz, 32 K/8 K/2 K 8 12 b SAR ADC 1 20 x UDB 9 CY 8 C 5465 67 MHz, 32 K/8 K/2 K 8 12 b SAR ADC 1 20 x UDB 9 Integration Analog-to-digital converter 2 Digital-to-analog converter 3 Comparator 1 001 -89679 Rev *F CY 8 C 5888 80 MHz, 256 K/64 K/2 K 8 20 b ΔƩ ADC 11, 2 x 12 b SAR ADC 1 24 x UDB 9, 99 -CSP 10 Fixed function 5 Switched capacitor/continuous time programmable analog block 4 Owner: JFMD BUM: GOPA Digital filter block 7 Controller area network 8 Flash KB/SRAM KB/EEPROM KB 6 Universal digital block Chip scale package 11 Delta-Sigma ADC Production Sampling Development Concept 9 10 Platform PSo. C Roadmap Status Availability QQYY

PSo. C Platform Packages Package Pins LQFP 48 PSo. C 1 PDIP QFN 8 20 28 16 24 32 40 PSo. C 3 PSo. C 4 SOIC 48 56 68 8 16 20 28 PSo. C 5 LP Cap. Sense Package SSOP TQFP Pins 8 16 20 24 28 32 48 44 PSo. C 1 PSo. C 3 64 100 30 PSo. C 5 LP Owner: JFMD BUM: GOPA Platform PSo. C Roadmap 72 µBGA 99 124 Cap. Sense 68 WLCSP PSo. C 4 001 -89679 Rev *F