Cyclone III FPGA Family Unprecedented combination of low

Meeting the Needs of Emerging High-Volume Applications • 2 – 20 K logic elements (LEs) • 295 -Kbits embedded RAM • DDR support • Nios® embedded processor 2002 • 5 – 70 K LEs • 1. 1 -Mbits embedded RAM • 150 18 x 18 multipliers for DSP • DDR 2 support • Nios II embedded processor 2004 • 50% lower power vs. Cyclone® II FPGAs • 5 – 120 K LEs • 4 -Mbits embedded RAM • 288 18 x 18 multipliers for DSP • Higher performance DDR 2 support • Nios II embedded processor 2007 © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 2

Cyclone III Key Architectural Features 65 -nm lowpower process Up to 4 -Mbit embedded memory Up to 535 flexible user I/O pins Parallel and serial configuration with new remote update feature © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 3 400 -Mbps external memory interfaces Up to 288 embedded multipliers for highthroughput DSP 5 – 120 K LEs Dynamically configurable phase-locked loops (PLLs)

System Integration System integration eases your design constraints - n Board space requirements Cost pressures Product obsolescence concerns Short development times FIFO UART DDR 2 UART CPU DSP Flash Cyclone III FPGAs— complete feature set for better integration over any other low-cost FPGA Do more with less! © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 4 ASSP DDR 2 Flash n

Power-Aware Design With Quartus II Software Design Entry Timing Constraints Automatic power reduction for maximum productivity Synthesis Place-and-route Timing, area, power optimization Power. Play Power Analyzer Up to 25% lower power Power-optimized design © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 5

Lowest-Power Low-Cost FPGAs Cyclone III family power reduction technique Process optimization Lower static power Lower dynamic power Power-aware design with Quartus II software 50+ Percent Power Reduction vs. Cyclone II FPGAs © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 6

DSP Advantages n Combination of logic, memory, and multipliers allows for efficient implementation of arithmetic DSP functions - Integrate multiple DSP devices into a single Cyclone III FPGA - Process multiple signal data streams at lower cost Gigamultiplies / sec per channel than dedicated DSP devices 80 70 60 50 DSP DSP 40 30 Up to 2 Multi 88 pliers 20 10 0 ADI TS 203 S @ 600 MHz TI C 6455 @ 1 GHz Altera EP 3 C 25 @ 260 MHz Altera EP 3 C 120 @ 223 MHz © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 7

Memory Optimizations n Increased memory block size - n Cyclone II family Allows for increased memory capacity Higher memory-to-logic ratio - Implement packet buffers Integrate larger data and instruction caches for embedded processors Integrate larger FIFO buffers 36 or M 4 K 4 Kbits 18 n Optimized memory-to-multiplier ratio for intensive processing applications Memory (Mbits) - 4. 5 4. 0 3. 5 3. 0 2. 5 2. 0 1. 5 1. 0 0. 5 0 Video line buffers Video and image processing Up to 4 Mb on-ch its ip memo ry Cyclone II FPGAs Cyclone III FPGAs 8 -10 K 20 -26 K 30 -40 K 50 -55 K 70 -120 K LEs or 18 Cyclone III family 36 or 18 5 K 36 © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 8 M 9 K 9 Kbits 36 or 18

Clocking Resources n n Clock routing resources - Up to 20 global clocks - Global clock routing can also be used for global signals - Powered down when not in use to save power Full-featured and robust PLLs - Up to four low-jitter (200 ps) PLLs - Five programmable outputs per PLL - Wide frequency range of 5 to 440 MHz - Dynamically change both frequency and phase - Cascadable to allow broader frequency generation Global clock networks Up to 20 networks per device Flexible and robust clocking resources to support higher system integration © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 9

I/O Pin Features LVDS Variety of I/O Standards up to 875 - HSTL, SSTL Class I and II Mbps - LVDS, RSDS, Mini-LVDS, PPDS Bank 3 - LVCMOS - LVTTL - LVPECL - PCI, PCI-X 3. 3 -V compatible On-chip termination Bank 8 Adjustable slew rates Eight banks of every device in the family - Each can implement any supported I/O standard DDR 2 Dedicated memory interfaces up to 400 Mbps - QDR II, DDR, and DDR 2 Bank 4 n n n Bank 1 n Bank 6 n Bank 5 Bank 2 n Bank 7 Complete flexibility to implement a wide variety of I/O standards © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 10

Memory Interfaces That Automatically Calibrate, Track, and Adjust Intellectual property (IP) auto calibrates for process differences - For both FPGA and memory - Removes timing uncertainties n Monitors voltage and temperature variations - Adjusts resynchronization phase (PLL output) - Does not interrupt operation - Supports DDR, DDR 2, QDR II memories Memory controller IP / / PHY IP / / Flexibility to use Auto-calibrating PHY Altera® or custom minimizes effort for memory controller reliable timing closure Increase productivity and minimize timing closure efforts © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 11 External memory n

New Configuration Features Update Control Logic Serial or Parallel Configuration Device • Multiboot feature allows multiple programming files to be loaded into the FPGA, and protect against remote system upgrade configuration failures • Remote system update no longer requires external host, saves board space Application n Application 1 Factory application © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 12

A Complete Solution Embedded soft-core processors Intellectual property Design software © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 13 Development kits

Nios II Embedded Processor n Choose the exact set of CPUs, peripherals, and memory you need for your application - Achieve over 160 DMIPs of performance - Build custom instructions - Accelerate with hardware—C 2 H compiler automatically converts C subroutines into hardware for Nios II embedded processor n Low cost - Integrate your peripherals and microprocessor into a single chip - Support for multiple processors in a single device - Implement a processor for $0. 25 of logic on a Cyclone III FPGA Available programmable logic Industry’s leading soft-core processor © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 14

Cyclone III Family Plan Device LEs M 9 K memory blocks Total memory (Mbits) 18 X 18 Multipliers PLLs Global clocks EP 3 C 5 5, 136 46 0. 4 23 2 10 EP 3 C 10 10, 320 46 0. 4 23 2 10 EP 3 C 16 15, 408 56 0. 5 56 4 20 EP 3 C 25 24, 624 66 0. 6 66 4 20 EP 3 C 40 39, 600 126 1. 1 126 4 20 EP 3 C 55 55, 856 260 2. 3 156 4 20 EP 3 C 80 81, 264 305 2. 7 244 4 20 EP 3 C 120 119, 088 432 3. 9 288 4 20 Notes: 1. Selected product lines are available in commercial, industrial, extended industrial, and automotive temperature variants. 2. Selected product lines/packages offer the following speed grades: -6 (fastest), -7, and -8. © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 15

Cyclone III Package Offerings E 144 M 164 Q 240 F 256 U 256 F 324 F 484 U 484 F 780 0. 5 mm 22 x 22 0. 5 mm 8 x 8 0. 5 mm 35 x 35 1. 0 mm 17 x 17 0. 8 mm 14 x 14 1. 0 mm 19 x 19 1. 0 mm 23 x 23 0. 8 mm 19 x 19 1. 0 mm 29 x 29 EP 3 C 5 94 106 182 EP 3 C 10 94 106 182 EP 3 C 16 84 92 160 168 EP 3 C 25 82 148 156 Device New ! 346 331 535 EP 3 C 55 327 377 EP 3 C 80 295 429 EP 3 C 120 283 EP 3 C 40 128 215 195 Denotes vertical migration support Optimized to offer the highest logic, memory, multiplier, and I/O resources © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 16 531

Technical Details © 2009 Altera Corporation— Public

Cyclone II LAB Structure Cyclone II Logic Array Block (LAB) 0 1 LUT 7 2 LUT 6 LUT 3 LUT 5 LUT 4 LUT LAB-Wide Control Block 8 9 LUT 15 LUT 10 LUT 14 LUT 13 LUT 11 LUT 12 LUT © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 18

Cyclone II Logic Element LUT Chain Carry In 0 Carry In 1 Register Chain Local Routing In 1 In 2 In 3 In 4 LUT REG General Routing Clock Carry Out 0 Out 1 Register Chain © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 19

Embedded Multiplier Functionality n n Up to 260 -MHz performance Supports full-precision 18 -bit or 9 -bit mode - One 18 -bit or two 9 -bit multipliers per block © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 20

On-Chip Memory Enhancements Feature Cyclone II (M 4 K) Cyclone III (M 9 K) Block Size 4 Kbits 9 Kbits 216 MHz 260 MHz New Data (“Flow Thru”) New Data or Old Data Yes Clock Enables 2 4 Increased Flexibility and Reduced Power Read and Write Enables 2 4 Increased Flexibility and Reduced Power Performance Dual-Port Read During Write Behavior Parity Bit Benefit Increased Memory Faster Performance Flexibility and Ease of Use Usability for High Reliability Apps © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 21

I/O Enhancements I/O Enhancement Benefit All Interfaces and Standards Supported on all Banks -Allows flexible I/O placement for easier PCB design reduced board area Enhanced LVDS Buffers -Eliminates external resistors for LVDS, RSDS, and mini-LVDS transmission -Increases LVDS interface performance – up to 875 Mbps (Rx) & 840 Mbps (Tx) Selectable Series OCT with Calibration -OCT Eliminates external resistors -Improves signal integrity and performance with selectable impedance matching -Calibration eliminates variations due to PVT Two Additional I/O Element Registers -Increases external interface performance -Improves Tco performance Adjustable Slew Rates -Improves signal integrity by slowing down edge rates on nonperformance critical I/O pins © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 22

All I/O Standards On All Banks Bank 7 Bank 3 Bank 4 Bank 1 Bank 6 Bank 8 Bank 5 Bank 2 © 2009 Altera Corporation— Public *HSTL-12 Class II is only supported on top and bottom banks ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 23

Supported I/O Standards Single-Ended I/O Standards 2. 5 -V SSTL Class I and II 1. 8 -V/1. 5 V/1. 2 -V HSTL I and II 3. 3 -V PCI Compatible 3. 3 -V PCI-X 1. 0 Compatible 3. 3 -V LVTTL 3. 0 -V/2. 5 -V/1. 8 -V LVTTL 3. 0 -V*/2. 5 -V/1. 8 -V/1. 5 -V/1. 2 -V LVCMOS Differential I/O Standards LVDS RSDS/Mini-LVDS Transmission LVPECL PCI Express* Serial Rapid. IO* Max Usage 167 MHz 200 MHz 167 MHz 66 MHz 100 MHz* 167 MHz DDR SDRAM DDR/DDR 2 SDRAM QDR II SRAM Embedded System Interface Max Comment 875 Mbps 440 Mbps 500 MHz 2. 5 Gbps 3. 125 Gbps High-Speed Serial High-Speed Clocks Per Channel *Different from BA presentation *IP cores available, requires external PHY devices © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 24

Enhanced LVDS Buffers n Dedicated LVDS Output Buffers on the left and right banks - Increased performance, 840 Mbps - No external resistors required n Improved LVDS Input Buffers on all banks - Increased performance, 875 Mbps LVDS Rx 875 Mbps LVDS Tx 840 Mbps LVDS Rx 875 Mbps LVDS Tx 640 Mbps © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 25

LVDS Pairs Reference © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 26

OCT With Calibration n n Output buffer impedance may vary slightly due to PVT With OCT Calibration, after configuration the output buffer impedance is automatically adjusted to match two external resisters (RUP & RDN), which are either 50 Ohms or 25 Ohms OCT Without Calibration OCT With Calibration VCCIO RUP 25 or 50 Ohm RDN © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 27

Two additional I/O element registers Improved Memory Performance and Flexibility © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 28

Slew Rate Control n n Available for all single ended I/O standards, with drive strengths of 8 m. A or more (except 3. 3 -V LVTTL) Selectable on a pin by pin basis, using the Quartus II Software assignment editor Three settings: fast, medium, slow Default is fast © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 29

Cyclone III – The Right Balance n The benefits of leading edge technology - 300 mm wafers - TSMC’s 65 nm low power process n With 3. 3 -V I/O support - 3. 3 -V I/O driven from 3. 3 -V VCCIO, or - 3. 3 -V I/O driven from 3. 0 -V VCCIO n As long as a few simple guidelines are followed - See AN 447 © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 30

Cyclone III External Memory Support Memory Standards n C 6 (MHz) C 7 (MHz) C 8 (MHz) Availability Col I/O Row I/O Quartus II software version DDR 1 SDRAM 167 150 133 125 6. 1 DDR 2 SDRAM 200 167 150 133 6. 1 QDRII SRAM 167 150 133 125 Q 2 ’ 06 All numbers are minimum frequencies achievable; maximum frequencies pending characterization © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 31

ALTMEMPHY Physical Interface n Soft megafunction included with all versions of the Quartus II software Self-calibrating at startup: - n Periodic calibration during operation - n n FPGA and memory device process changes System uncertainties Voltage and temperature changes Push button timing closure Better performance for fast and slow speed grade devices Cyclone III FPGA Memory Controller Soft IP Altera or Custom Memory Controller / / PLL ALTMEM- PHY Soft IP / / External Memory n Autocalibrating PHY Minimizes Effort for Timing Closure © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 32

Timing Margins Are Shrinking Align Clock Capture Phase Here DQS DQ (First Data Valid) DQ (Last Data Valid) Data Valid at Memory Data Valid at FPGA Board Uncertainties Setup & Hold Time Internal Skew between DQS & DQ Total Timing Margin © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 33

Additional Uncertainties n n Temperature and voltage changes Process variations over time Memory vendor changes Board layout changes Data Valid at FPGA Setup & Hold Time Internal Skew between DQS & DQ Total Timing Margin © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 34

PLL Dynamic Phase Adjustment n n Dynamic adjustment of PLL phase setting Increase/decrease 1 step at a time - Step increments depend on PLL configuration inclk 0 C 0 Phasecounterselect[3: 0] Phasedone Phaseupdown PLL Phasestep © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 35 Locked

Calibration at Startup Write Training Pattern Phase Pin Set PLL Phase Read DQ and Compare to Training Pattern (repeat for all pins) Set Optimum Clock Phase PHY adapts to your system! © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 36

Periodic Calibration n Data capture and measurement of a representative mimic path delay every 128 ms - Path delay may change due to voltage and temperature changes - Assumption: Data Valid window drift due to temperature and voltage similar to delay change of representative path n Non-Intrusive dynamic phase adjustment Measure delay changes of mimic path Data Valid Window Shifts Due to Voltage and Temp. Changes 0 15 30………. . . . 330 345 360 T=1 Re-Set Optimum Clock Phase T=2 T=500 © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 37

Signal Integrity n Series On-Chip Termination - Match output driver impedance to trace impedance - Calibrated on power up for process, temperature, and voltage variations n Adjustable Slew Rates - Choose slower slew rates to lower simultaneously switching output (SSO) effects n IBIS models for board simulation - Pending characterization © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 38

Flexible PCB Layout n Interfaces available on all sides © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 39

Clock Networks & PLLs Overview n Flexible clock management resources maximize system integration capabilities - PLL features l Dynamic phase adjustments enable self-calibrating external memory controllers l Reconfiguration enables display applications where the input frequency is unknown l Generate up to 10 internal clocks and 2 external clocks from a single clock source l 5 outputs per PLL combined with new IP enables x 72 DDR 2 interfaces using just 1 PLL - Unused clock networks are turned off to minimize power consumption - Global clock networks double as low skew, high fanout control signals © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 40

Clock Networks & PLLs Overview n Up to 20 Global Clocks Per Device n Dual purpose as high fan out control signals 4 PLL 3 GCLK Mux PLL 2 GCLK [14: 10] 4 GCLK Mux GCLK [0: 4] GCLK [9: 5] GCLK Mux 4 GCLK [15: 19] PLL 1 © 2009 Altera Corporation— Public GCLK Mux 4 PLL 4 ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 41

Cyclone III PLL Functions n n n Clock Multiplication & Division Clock Synthesis Phase Alignment & Phase Shift Output C 0 Pin Clock Switchover C 0 Clock Inputs [1. . 0] N PFD CP LF VCO C 1 C 2 Global Clock C[4. . 0] Network M C 3 Feedback C 4 Reconfigurable in user mode © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 42

Cascading PLLs Supply a clk to other devices Cyclone III PLL GCLK MUX 5 Clock Networks per PLL 5 Cascade through global clock network Cyclone III PLL GCLK MUX © 2009 Altera Corporation— Public 5 Output Pin Supply a clk to other devices Up to 10 internal & 2 external clocks from 1 clock source Finer resolution multiplication/division & phase shifting Clean up low performance and noisy external clock sources ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 43

PLL Dynamic Phase Adjustment n n Dynamic adjustment of PLL phase setting Increase/decrease 1 step at a time - Step increments depend on PLL configuration inclk 0 C 0 Phasecounterselect[3: 0] Phasedone Phaseupdown PLL Locked Phasestep Enables Auto-Calibrating PHY for External Memory Interfaces © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 44

Clock Switch Over n n Automatically switch from 1 clock to another in the event a clock stops Manually switch from 1 clock source to another Clock Switch Over Control Clock pins or GCLK network CLK MUX Cyclone III PLL © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 45

Compensation Modes PLL Mode Description Source Synchronous Clock-to-data relationship at input pin (setup/hold) maintained at the IOE register No Compensation No compensation for best jitter performance Normal Input clock delay fully compensated for alignment with clock at IOE or core register Zero Delay Buffer Input clock aligned with dedicated external clock output © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 46

PLL Feature Comparison Cyclone III Advantages Number of PLLs 2 – 4 Outputs per PLL 3 5 Up to 8 additional global clocks driven by PLLs Number of Global Clocks 8 – 16 10 – 20 Combine required clock signals into fewer PLLs Min, Max Frequency (MHz) 10 – 400 5 – 440 Broader range improves system flexibility Dynamic Reconfiguration No Frequency and Phase Improve system performance by removing device downtime Cascadable No Yes Increase PCB routing flexibility Same © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 47

Cyclone III Configuration Overview n Comprehensive configuration and remote system upgrade solution - Simple, easy to use, & low cost - Available with option does not require external host - Altera serial configuration devices available for all densities n Commodity Flash configuration - Free configuration solution if extra memory is available in a parallel Flash already on board n Cyclone III serial & parallel Flash loader - In system programming of serial and parallel configuration devices through Cyclone III JTAG port © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 48

What’s New in Cyclone III Configuration? Active Parallel - Configuration with commodity parallel Flash already on board Remote System Upgrade - No external host required Fast-On - Option to reduce maximum POR time to 9 ms to meet automotive 100 ms “wake up” time requirements Fast Passive Parallel - Fastest configuration option Allows 100 MHz clock with x 8 data width without a separate controller - First time for any Altera FPGA - Available with Active Serial or Active Parallel configuration mode - © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 49

Configuration Mode Overview Programming Mode Cyclone III Active Serial Active Parallel Passive Serial Fast Passive Parallel JTAG Cyclone I & II Stratix II Stratix Remote Update First time for Cyclone Family FPGAs n n Active: Controller in FPGA & Clock is from FPGA Passive: Controller outside of FPGA & Clock is supplied from outside controller © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 50

Understanding Configuration Timing Vcc ramp up time POR Time Configuration Time Cyclone III Fast: 3 to 9 ms Depends on configuration mode, clock frequency & device density in user mode operation Slow: 50 to 200 ms “Wake-up” Time Total time before Cyclone III is operational from power up n n n Application with fast “Wake-up” time specification needs to utilize fast POR time and fast configuration modes POR time and configuration time user configurable with mode select pins(MSEL 3. . 0) Fast POR option requires fast* Vcc ramp time needs to be faster than POR Time. Specification will be determined after characterization ** Only major timings are shown above © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 51

Configuration Mode Comparison Ease of Usea Config Speedb Additional # Chips Required # of Cyclone III Pinsc Data Compression Remote Upgrade Active Serial 1 292 ms 1 4 Active Parallel 2 48 ms 1 47 Passive Serial 3 117 ms 2 2 Fast Passive Parallel 4 38 ms 2 9 JTAGd 5 210 ms 2 4 Configuration Mode a. Ease of Use: Subjective rating based on number of chips, number of I/Os required, and additional knowledge requirement (1 being the easiest solution) b. Benchmark based on 3 C 80 at maximum frequency for each mode c. Pin count excluding MSEL 3. . 0, n. Status, CONF_Done, n. CE, and n. CEO © 2009 Altera Corporation— Public d. JTAG using an external controller and a Flash device ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 52

Configuration File Size & Time Device File Size* (Mbits) Compressed Size (Mbits) AS** (ms) AP (ms) FPP (ms) EP 3 C 5 3. 3 1. 9 49 5 4 EP 3 C 10 3. 3 1. 9 49 5 4 EP 3 C 16 4. 3 2. 4 63 7 6 EP 3 C 25 6. 2 3. 4 90 10 8 EP 3 C 40 10. 0 5. 6 146 16 13 EP 3 C 55 15. 3 8. 5 222 25 20 EP 3 C 80 20. 0 11. 1 292 33 26 EP 3 C 120 29. 1 16. 2 424 48 38 Clock Frequency for Active Serial (AS): 40 Mhz***, Active Parallel (AP): 40 Mhz***, Fast Passive Parallel (FPP): 100 Mhz * Preliminary information ** Configuration Time using compressed data for AS mode *** Max/Typ/Min = 40 Mhz/30 Mhz/20 Mhz, configuration times can be up to 2 X longer than values in table for AS and AP modes © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 53

Programming Flash in System n Program or examine Flash device from Quartus II programmer window - Cyclone III works as a Flash programmer with Flash loader SOF - Quartus II downloads SOF automatically & programs Flash n Eliminates additional hardware and software for on board Flash programming - Unique tool for Altera USB Flash Programmer* JTAG Cyclone III Parallel Flash Or Serial Configuration Device Flash Loader SOF USB User board © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 54 * Byte. Blaster & Ethernet. Blaster works identically

Cyclone III Remote System Upgrade n n Allows multiple new application images in addition to factory image Built in recovery circuitry loads factory image if upgrade image fails to load No external host or processor required Customize with Nios II or user-defined control logic © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 55

Remote System Upgrade n Utilize in application where time to market is critical - Ship initial product with minimum feature set - Remotely upgrade system without system being down due to upgrade failure - Can be used for bug fix and/or upgrade application Configuration Device Cyclone III Remote Source Send Update 1 Control Logic Recovery Circuitry 2 Application n Store Update Application 1 Factory Application 3 Update Cyclone III Device © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U. S. Pat. & Tm. Off. and Altera marks in and outside the U. S. 56