CYCL E Instruction ADD SUB NAND SHIFT ORI
CYCL E Instruction ADD, SUB, NAND SHIFT ORI LOAD STORE 1 [IR] = Mem[ [PC] ] [PC] = [PC] + 1 2 [Op. A] = RF[ [IR 7. . 6] ] [Op. B] = RF[ [IR 5. . 4] ] 3 [ALUout] = [Op. A] op [Op. B] 4 RF[ [IR 7. . 6] ] = [ALUout] 5 [ALUout] = [Op. A] shift [Op. A] = RF [1] Imm 3 [MDR] = Mem[ [Op. B] ] [ALUout] = [R 1] RF[[IR 7. . 6]] = [MDR] OR Imm 5 RF[ 1 ] = [ALUout] MEM[[Op. B] = [Op. A] BPZ if (N’) PC = PC + SE(Imm 4) BZ BNZ if (Z) if (‘Z) PC = PC + SE(Imm 4)
8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 data 2 8 1 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PCwrite 8 1 ALU 2 ADDR PC 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
ADD Op. A Op. B • Read mem[PC] • Decode • Read Op. A, Read Op. B – Op. A = inst 7, 6 – Op. B = inst 5, 4 • • tmp = Op. A + Op. B Op. A = tmp 7 set Z, N Op. A PC = PC + 1 6 5 4 3 2 1 0 Op. A Op. B 0 1 0 0
CYCLE 1: IR = Mem[PC] 8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
CYCLE 2: Decode 8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
CYCLE 3: Op. A = RF[IR 7, 6] & Op. B = RF[IR 5, 4] 8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
CYCLE 4: Alu. Out = Op. A + Op. B, Update Z & N 8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 data 2 8 1 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PCwrite 8 1 ALU 2 ADDR PC 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
CYCLE 5: RF[IR 7, 6] = Alu. Out 8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 R 1 1 IR 5 -4 2 reg 2 RF 8 data 2 1 regw Memory Data_in dataw ALU 8 R 2 000 8 1 8 001 8 8 Data_out MDR PCwrite 8 1 ALU 2 ADDR PC 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
CYCLE 6: PC = PC + 1 8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 R 1 1 IR 5 -4 2 reg 2 RF 8 data 2 1 regw Memory Data_in dataw ALU 8 R 2 000 8 1 8 001 8 8 Data_out MDR PCwrite 8 1 ALU 2 ADDR PC 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
CYCLE 1: IR = Mem[PC] CYCLE 2: Decode CYCLE 3: Oo. A = RF[IR 7, 6] & Op. B = RF[IR 5, 4] CYCLE 4: Alu. Out = Op. A + Op. B, Update Z & N CYCLE 5: RF[IR 7, 6] = Alu. Out CYCLE 6: PC = PC + 1
8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
SUB Op. A Op. B • Read mem[PC] • Decode • Read Op. A, Read Op. B – Op. A = inst 7, 6 – Op. B = inst 5, 4 • • tmp = Op. A-Op. B Op. A = tmp set Z, N PC = PC + 1 7 6 5 4 3 2 1 0 Op. A Op. B 0 1 1 0
8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
NAND Op. A Op. B • Read mem[PC] • Decode • Read Op. A, Read Op. B – Op. A = inst 7, 6 – Op. B = inst 5, 4 • • tmp = Op. A nand Op. B 7 Op. A = tmp Op. A set Z, N PC = PC + 1 6 5 4 3 2 1 0 Op. A Op. B 1 0 0 0
8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
ORI imm 5 • • Read mem[PC] Decode Read r 1 tmp = r 1 or ZE(Imm 5) – Imm 5 = Inst 7, 3 • r 1 = tmp • set Z, N • PC = PC + 1 7 6 5 4 3 2 1 0 IMM 5_ 4 IMM 5_ 3 IMM 5_ 2 IMM 5_ 1 IMM 5_ 0 1 1 1
8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
LOAD Op. A (Op. B) • • • Read mem[PC] Decode Read Op. B tmp = Mem(Op. B) Op. A = tmp PC = PC + 1 7 6 5 4 3 2 1 0 Op. A Op. B 0 0
8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
Store Op. A (Op. B) • • • Read mem[PC] Decode Read Op. B, Op. A Mem(Op. B) = Op. A PC = PC + 1 7 6 5 4 3 2 1 0 Op. A Op. B 0 0 1 0
8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout R 1 Sel Op. ASel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
BZ Imm 4 • • Read mem[PC] Decode if (Z is true) PC = PC + 1 + SE (Imm 4) else PC = PC + 1 7 6 5 4 3 2 1 0 IMM 4_ 3 IMM 4_ 2 IMM 4_ 1 IMM 4_ 0 0 1
8 8 ALU 1 RFWrite 0 IR 6 -7 0 0 Mem. Read 1 Mem. Write IR 8 data 1 reg 1 2 Addr. Sel 8 2 Op A 1 IR 5 -4 2 reg 2 RF 8 ADDR PCwrite 8 8 regw Memory Data_in dataw ALU 8 Op B 000 1 8 001 8 8 Data_out MDR PC 1 ALU 2 data 2 1 8 ALUop 3 8 ALUout Op. ASel R 1 Sel IRload Imm 4 4 Imm 5 5 Imm 3 SE ZE 8 010 8 011 ZE 100 Reg. In MDRload Flag. Write N Z 8
Op. ASel R 1 Sel RFWrite Inst 7 -6 2 Inst 5 -4 PCSel 0 1 1 ALU 2 2 reg 2 RF ALU 8 00 8 8 PC 8 data 2 ADDR 8 8 data 1 reg 1 2 1 ALUop 3 8 0 IM 1 Inst 7 -3 INST PCwrite regw 8 Inst 5 -3 Imm 4 4 8 Inst 7 -4 8 1 Imm 5 Imm 3 5 dataw ZE 8 8 01 ZE 10 Flag. Write N Z 11 SE Reg. In 0 1 8 Mem. Read 8 Mem. Write 8 ADDR 8 Data Memory 8 8 Data_in 8 Data_out 8
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