CSE 670 DESIGN OF EMBEDDED SYSTEMS USING FPGA

CSE: - 670 DESIGN OF EMBEDDED SYSTEMS USING FPGA. PROFESSOR: Dr. RICHARD E. HASKELL. MIDTERM EXAM. NAME: - RAVI D. SHAH

ALGORITHM. Accept the input (number whose factorial is desired) from switches and store it in R 2 making wld = ‘ 1’ for display. Provide the first number using which the algorithm starts. (i. e. 1) using the switches and store it in R 0 and R 1 making wld = ‘ 1’ for display. Now bring R 1 to input a of the alu and perform multiplication. Store the answer in R 1.

1. Bring R 0 to input a of the alu and perform a+b. Now input b of the alu has the value of a+b on it. Now bring R 2 to input a of the alu and perform a-b. If z = ‘ 0’ then bring R 1 again to input a of the alu and perform multiplication and so on. If z = ‘ 1’ perform multiplication, store the answer in R 2 register and keep displaying it untill the new number is entered.

DATAPATH AND CONTROL UNIT Components used in the Datapath: - Registers, Multiplexer, ALU, Binary to BCD convertor and BCD to seven segment convertor for display. Control Unit: - It employs the state machine approach with a total of 13 states communicating with each other.

ADVANTAGES OF THE ALGORITHM. Can be a part of any Embedded System where multiply and add operation is being performed like in a correlator in a Global Positioning System. Implemented through the state machine approach which provides clear and perfect communication between the states, which facilitates both debugging and implementation. With more display options in terms of the number of LCD displays it is a smooth implementation for finding factorial of as large a number as required.