CSE 431 Computer Architecture Fall 2005 Lecture 2021

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CSE 431 Computer Architecture Fall 2005 Lecture 20&21. Improving Cache Performance Mary Jane Irwin

CSE 431 Computer Architecture Fall 2005 Lecture 20&21. Improving Cache Performance Mary Jane Irwin ( www. cse. psu. edu/~mji ) www. cse. psu. edu/~cg 431 [Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005] CSE 431 L 20&21 Improving Cache Performance. 1 Irwin, PSU, 2005

Review: The Memory Hierarchy q Take advantage of the principle of locality to present

Review: The Memory Hierarchy q Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology Processor 4 -8 bytes (word) Increasing distance from the processor in access time L 1$ 8 -32 bytes (block) L 2$ 1 to 4 blocks Main Memory Inclusive– what is in L 1$ is a subset of what is in L 2$ is a subset of what is in MM that is a subset of is in SM 1, 024+ bytes (disk sector = page) Secondary Memory (Relative) size of the memory at each level CSE 431 L 20&21 Improving Cache Performance. 2 Irwin, PSU, 2005

Review: Principle of Locality q Temporal Locality l q Spatial Locality l q Keep

Review: Principle of Locality q Temporal Locality l q Spatial Locality l q Keep most recently accessed data items closer to the processor Move blocks consisting of contiguous words to the upper levels To Processor Upper Level Memory From Processor Lower Level Memory Blk X Blk Y Hit Time << Miss Penalty l Hit: data appears in some block in the upper level (Blk X) - Hit Rate: the fraction of accesses found in the upper level - Hit Time: RAM access time + Time to determine hit/miss l Miss: data needs to be retrieve from a lower level block (Blk Y) - Miss Rate = 1 - (Hit Rate) - Miss Penalty: Time to replace a block in the upper level with a block from the lower level + Time to deliver this block’s word to the processor - Miss Types: Compulsory, Conflict, Capacity CSE 431 L 20&21 Improving Cache Performance. 3 Irwin, PSU, 2005

Measuring Cache Performance q Assuming cache hit costs are included as part of the

Measuring Cache Performance q Assuming cache hit costs are included as part of the normal CPU execution cycle, then CPU time = IC × CPI × CC = IC × (CPIideal + Memory-stall cycles) × CC CPIstall q Memory-stall cycles come from cache misses (a sum of read-stalls and write-stalls) Read-stall cycles = reads/program × read miss rate × read miss penalty Write-stall cycles = (writes/program × write miss rate × write miss penalty) + write buffer stalls q For write-through caches, we can simplify this to Memory-stall cycles = miss rate × miss penalty CSE 431 L 20&21 Improving Cache Performance. 4 Irwin, PSU, 2005

Review: The “Memory Wall” CSE 431 L 20&21 Improving Cache Performance. 5 Clocks per

Review: The “Memory Wall” CSE 431 L 20&21 Improving Cache Performance. 5 Clocks per DRAM access Logic vs DRAM speed gap continues to grow Clocks per instruction q Irwin, PSU, 2005

Impacts of Cache Performance q q Relative cache penalty increases as processor performance improves

Impacts of Cache Performance q q Relative cache penalty increases as processor performance improves (faster clock rate and/or lower CPI) l The memory speed is unlikely to improve as fast as processor cycle time. When calculating CPIstall, the cache miss penalty is measured in processor clock cycles needed to handle a miss l The lower the CPIideal, the more pronounced the impact of stalls A processor with a CPIideal of 2, a 100 cycle miss penalty, 36% load/store instr’s, and 2% I$ and 4% D$ miss rates Memory-stall cycles = 2% × 100 + 36% × 4% × 100 = 3. 44 So CPIstalls = 2 + 3. 44 = 5. 44 q What if the CPIideal is reduced to 1? 0. 5? 0. 25? q What if the processor clock rate is doubled (doubling the miss penalty)? CSE 431 L 20&21 Improving Cache Performance. 6 Irwin, PSU, 2005

Reducing Cache Miss Rates #1 1. Allow more flexible block placement q In a

Reducing Cache Miss Rates #1 1. Allow more flexible block placement q In a direct mapped cache a memory block maps to exactly one cache block q At the other extreme, could allow a memory block to be mapped to any cache block – fully associative cache q A compromise is to divide the cache into sets each of which consists of n “ways” (n-way set associative). A memory block maps to a unique set (specified by the index field) and can be placed in any way of that set (so there are n choices) (block address) modulo (# sets in the cache) CSE 431 L 20&21 Improving Cache Performance. 7 Irwin, PSU, 2005

Set Associative Cache Example Cache Way Set V 0 0 1 1 0 1

Set Associative Cache Example Cache Way Set V 0 0 1 1 0 1 Tag Data Q 1: Is it there? Compare all the cache tags in the set to the high order 3 memory address bits to tell if the memory block is in the cache CSE 431 L 20&21 Improving Cache Performance. 8 Main Memory 0000 xx 0001 xx Two low order bits define the byte in the 0010 xx word (32 -b words) 0011 xx One word blocks 0100 xx 0101 xx 0110 xx 0111 xx Q 2: How do we find it? 1000 xx 1001 xx Use next 1 low order 1010 xx memory address bit to 1011 xx 1100 xx determine which 1101 xx cache set (i. e. , modulo 1110 xx the number of sets in 1111 xx the cache) Irwin, PSU, 2005

Another Reference String Mapping q Consider the main memory word reference string Start with

Another Reference String Mapping q Consider the main memory word reference string Start with an empty cache - all blocks initially marked as not valid 0 miss 000 l q Mem(0) 0 4 0 4 4 miss 0 hit 4 hit 000 Mem(0) 010 Mem(4) 8 requests, 2 misses Solves the ping pong effect in a direct mapped cache due to conflict misses since now two memory locations that map into the same cache set can co-exist! CSE 431 L 20&21 Improving Cache Performance. 10 Irwin, PSU, 2005

Four-Way Set Associative Cache q 28 = 256 sets each with four ways (each

Four-Way Set Associative Cache q 28 = 256 sets each with four ways (each with one block) 31 30 . . . 13 12 11 22 Tag Index V Tag 0 1 2. . . 253 254 255 V Tag Data 0 1 2. . . 253 254 255 . . . 8 V Tag Data Byte offset 2 1 0 V Tag Data 0 1 2. . . 253 254 255 32 4 x 1 select Hit CSE 431 L 20&21 Improving Cache Performance. 11 Data Irwin, PSU, 2005

Range of Set Associative Caches q For a fixed size cache, each increase by

Range of Set Associative Caches q For a fixed size cache, each increase by a factor of two in associativity doubles the number of blocks per set (i. e. , the number or ways) and halves the number of sets – decreases the size of the index by 1 bit and increases the size of the tag by 1 bit Used for tag compare Tag Decreasing associativity Direct mapped (only one way) Smaller tags CSE 431 L 20&21 Improving Cache Performance. 13 Selects the set Index Selects the word in the block Block offset Byte offset Increasing associativity Fully associative (only one set) Tag is all the bits except block and byte offset Irwin, PSU, 2005

Costs of Set Associative Caches q When a miss occurs, which way’s block do

Costs of Set Associative Caches q When a miss occurs, which way’s block do we pick for replacement? l Least Recently Used (LRU): the block replaced is the one that has been unused for the longest time - Must have hardware to keep track of when each way’s block was used relative to the other blocks in the set - For 2 -way set associative, takes one bit per set → set the bit when a block is referenced (and reset the other way’s bit) q N-way set associative cache costs l N comparators (delay and area) l MUX delay (set selection) before data is available l Data available after set selection (and Hit/Miss decision). In a direct mapped cache, the cache block is available before the Hit/Miss decision - So its not possible to just assume a hit and continue and recover later if it was a miss CSE 431 L 20&21 Improving Cache Performance. 14 Irwin, PSU, 2005

Benefits of Set Associative Caches q The choice of direct mapped or set associative

Benefits of Set Associative Caches q The choice of direct mapped or set associative depends on the cost of a miss versus the cost of implementation Data from Hennessy & Patterson, Computer Architecture, 2003 q Largest gains are in going from direct mapped to 2 -way (20%+ reduction in miss rate) CSE 431 L 20&21 Improving Cache Performance. 15 Irwin, PSU, 2005

Reducing Cache Miss Rates #2 2. Use multiple levels of caches q With advancing

Reducing Cache Miss Rates #2 2. Use multiple levels of caches q With advancing technology have more than enough room on the die for bigger L 1 caches or for a second level of caches – normally a unified L 2 cache (i. e. , it holds both instructions and data) and in some cases even a unified L 3 cache q For our example, CPIideal of 2, 100 cycle miss penalty (to main memory), 36% load/stores, a 2% (4%) L 1 I$ (D$) miss rate, add a UL 2$ that has a 25 cycle miss penalty and a 0. 5% miss rate CPIstalls = 2 +. 02× 25 +. 36×. 04× 25 +. 005× 100 +. 36×. 005× 100 = 3. 54 (as compared to 5. 44 with no L 2$) CSE 431 L 20&21 Improving Cache Performance. 16 Irwin, PSU, 2005

Multilevel Cache Design Considerations q Design considerations for L 1 and L 2 caches

Multilevel Cache Design Considerations q Design considerations for L 1 and L 2 caches are very different l Primary cache should focus on minimizing hit time in support of a shorter clock cycle - Smaller with smaller block sizes l Secondary cache(s) should focus on reducing miss rate to reduce the penalty of long main memory access times - Larger with larger block sizes q The miss penalty of the L 1 cache is significantly reduced by the presence of an L 2 cache – so it can be smaller (i. e. , faster) but have a higher miss rate q For the L 2 cache, hit time is less important than miss rate l The L 2$ hit time determines L 1$’s miss penalty l L 2$ local miss rate >> than the global miss rate CSE 431 L 20&21 Improving Cache Performance. 17 Irwin, PSU, 2005

Key Cache Design Parameters L 1 typical L 2 typical Total size (blocks) 250

Key Cache Design Parameters L 1 typical L 2 typical Total size (blocks) 250 to 2000 4000 to 250, 000 Total size (KB) 16 to 64 500 to 8000 Block size (B) 32 to 64 32 to 128 Miss penalty (clocks) 10 to 25 100 to 1000 Miss rates (global for L 2) 2% to 5% 0. 1% to 2% CSE 431 L 20&21 Improving Cache Performance. 18 Irwin, PSU, 2005

Two Machines’ Cache Parameters Intel P 4 AMD Opteron L 1 organization Split I$

Two Machines’ Cache Parameters Intel P 4 AMD Opteron L 1 organization Split I$ and D$ L 1 cache size 8 KB for D$, 96 KB for trace cache (~I$) 64 KB for each of I$ and D$ L 1 block size 64 bytes L 1 associativity 4 -way set assoc. 2 -way set assoc. L 1 replacement ~ LRU L 1 write policy write-through write-back L 2 organization Unified L 2 cache size 512 KB 1024 KB (1 MB) L 2 block size 128 bytes 64 bytes L 2 associativity 8 -way set assoc. 16 -way set assoc. L 2 replacement ~LRU L 2 write policy write-back CSE 431 L 20&21 Improving Cache Performance. 19 Irwin, PSU, 2005

4 Questions for the Memory Hierarchy q Q 1: Where can a block be

4 Questions for the Memory Hierarchy q Q 1: Where can a block be placed in the upper level? (Block placement) q Q 2: How is a block found if it is in the upper level? (Block identification) q Q 3: Which block should be replaced on a miss? (Block replacement) q Q 4: What happens on a write? (Write strategy) CSE 431 L 20&21 Improving Cache Performance. 20 Irwin, PSU, 2005

Q 1&Q 2: Where can a block be placed/found? # of sets Direct mapped

Q 1&Q 2: Where can a block be placed/found? # of sets Direct mapped # of blocks in cache Set associative (# of blocks in cache)/ associativity Fully associative 1 Location method Direct mapped Index Set associative Index the set; compare set’s tags Fully associative Compare all blocks tags CSE 431 L 20&21 Improving Cache Performance. 21 Blocks per set 1 Associativity (typically 2 to 16) # of blocks in cache # of comparisons 1 Degree of associativity # of blocks Irwin, PSU, 2005

Q 3: Which block should be replaced on a miss? q Easy for direct

Q 3: Which block should be replaced on a miss? q Easy for direct mapped – only one choice q Set associative or fully associative l Random l LRU (Least Recently Used) q For a 2 -way set associative cache, random replacement has a miss rate about 1. 1 times higher than LRU. q LRU is too costly to implement for high levels of associativity (> 4 -way) since tracking the usage information is costly CSE 431 L 20&21 Improving Cache Performance. 22 Irwin, PSU, 2005

Q 4: What happens on a write? q Write-through – The information is written

Q 4: What happens on a write? q Write-through – The information is written to both the block in the cache and to the block in the next lower level of the memory hierarchy l q Write-back – The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. l q Write-through is always combined with a write buffer so write waits to lower level memory can be eliminated (as long as the write buffer doesn’t fill) Need a dirty bit to keep track of whether the block is clean or dirty Pros and cons of each? l Write-through: read misses don’t result in writes (so are simpler and cheaper) l Write-back: repeated writes require only one write to lower level CSE 431 L 20&21 Improving Cache Performance. 23 Irwin, PSU, 2005

Improving Cache Performance 0. Reduce the time to hit in the cache l smaller

Improving Cache Performance 0. Reduce the time to hit in the cache l smaller cache l direct mapped cache l smaller blocks l for writes - no write allocate – no “hit” on cache, just write to write buffer - write allocate – to avoid two cycles (first check for hit, then write) pipeline writes via a delayed write buffer to cache 1. Reduce the miss rate l l bigger cache more flexible placement (increase associativity) larger blocks (16 to 64 bytes typical) victim cache – small buffer holding most recently discarded blocks CSE 431 L 20&21 Improving Cache Performance. 24 Irwin, PSU, 2005

Improving Cache Performance 2. Reduce the miss penalty l l l smaller blocks use

Improving Cache Performance 2. Reduce the miss penalty l l l smaller blocks use a write buffer to hold dirty blocks being replaced so don’t have to wait for the write to complete before reading check write buffer (and/or victim cache) on read miss – may get lucky for large blocks fetch critical word first use multiple cache levels – L 2 cache not tied to CPU clock rate faster backing store/improved memory bandwidth - wider buses - memory interleaving, page mode DRAMs CSE 431 L 20&21 Improving Cache Performance. 25 Irwin, PSU, 2005

Summary: The Cache Design Space q q Several interacting dimensions l cache size l

Summary: The Cache Design Space q q Several interacting dimensions l cache size l block size l associativity l replacement policy l write-through vs write-back l write allocation Cache Size Associativity Block Size The optimal choice is a compromise l depends on access characteristics - workload Bad - use (I-cache, D-cache, TLB) l q depends on technology / cost Simplicity often wins CSE 431 L 20&21 Improving Cache Performance. 26 Good Factor A Less Factor B More Irwin, PSU, 2005

Next Lecture and Reminders q Next lecture - Reading assignment – PH 7. 4

Next Lecture and Reminders q Next lecture - Reading assignment – PH 7. 4 q Reminders l HW 4 due November 8 rd l Check grade posting on-line (by your midterm exam number) for correctness l Final exam (tentatively) schedule - Tuesday, December 13 th, 2: 30 -4: 20, Location TBD CSE 431 L 20&21 Improving Cache Performance. 27 Irwin, PSU, 2005