CSCE 430830 Computer Architecture Basic Pipelining Performance Adopted

CSCE 430/830 Computer Architecture Basic Pipelining & Performance Adopted from Professor David Patterson Electrical Engineering and Computer Sciences University of California, Berkeley

Outline • • MIPS – An ISA for Pipelining 5 stage pipelining Structural and Data Hazards Forwarding Branch Schemes Exceptions and Interrupts Conclusion 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 2

A "Typical" RISC ISA • • 32 bit fixed format instruction (3 formats) 32 32 bit GPR (R 0 contains zero, DP take pair) 3 address, reg arithmetic instruction Single address mode for load/store: base + displacement – no indirection • Simple branch conditions • Delayed branch see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM Power. PC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 3

Example: MIPS ( MIPS) Register-Register 31 26 25 Op 21 20 Rs 1 16 15 Rs 2 11 10 6 5 Rd 0 Opx Register-Immediate 31 26 25 Op 21 20 Rs 1 16 15 Rd immediate 0 Branch 31 26 25 Op 21 20 Rs 1 16 15 Rs 2/Opx immediate 0 Jump / Call 31 26 25 Op 12/3/2020 target CSCE 430/830, Basic Pipelining & Performance 0 4

Datapath vs Control Datapath Controller signals Control Points • Datapath: Storage, FU, interconnect sufficient to perform the desired functions – Inputs are Control Points – Outputs are signals • Controller: State machine to orchestrate operation on the data path – Based on desired function and signals 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 5

Approaching an ISA • Instruction Set Architecture – Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing • Meaning of each instruction is described by RTL (Register Transfer Language) on architected registers and memory • Given technology constraints assemble adequate datapath – – Architected storage mapped to actual storage Function units to do all the required operations Possible additional storage (eg. MAR, MBR, …) Interconnect to move information among regs and FUs • Map each instruction to sequence of RTLs • Collate sequences into symbolic controller state transition diagram (STD) • Lower symbolic STD to control points • Implement controller 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 6

5 Steps of MIPS Datapath Figure A. 2, Page A 8 Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Next SEQ PC Adder 4 L M D MUX Data Memory ALU Imm MUX RD Reg File Inst Memory Address IR <= mem[PC]; Zero? RS 1 RS 2 Write Back MUX Next PC Memory Access Sign Extend PC <= PC + 4 Reg[IRrd] <= Reg[IRrs 1] op. IRop Reg[IRrs 2] 12/3/2020 WB Data CSCE 430/830, Basic Pipelining & Performance 7

5 Steps of MIPS Datapath Figure A. 3, Page A 9 Execute Addr. Calc Instr. Decode Reg. Fetch Next SEQ PC Adder 4 Zero? RS 1 MUX MEM/WB Data Memory EX/MEM A <= Reg[IRrs 1]; Imm ALU PC <= PC + 4 MUX IR <= mem[PC]; ID/EX RD Reg File IF/ID Memory Address RS 2 Write Back MUX Next PC Memory Access WB Data Instruction Fetch Sign Extend RD RD RD B <= Reg[IRrs 2] rslt <= A op. IRop B WB <= result 12/3/2020 Reg[IRrd] <= WB CSCE 430/830, Basic Pipelining & Performance 8

Inst. Set Processor Controller IR <= mem[PC]; PC <= PC + 4 JSR A <= Reg[IRrs 1]; JR br if bop(A, b) Ifetch op. Fetch DCD ST B <= Reg[IRrs 2] jmp RR PC <= IRjaddr r <= A op. IRop B RI LD r <= A op. IRop IRim r <= A + IRim WB <= r WB <= Mem[r] PC <= PC+IRim WB <= r Reg[IRrd] <= WB CSCE 430/830, Basic Pipelining & Performance Reg[IRrd] <= WB 9

5 Steps of MIPS Datapath Figure A. 3, Page A 9 Execute Addr. Calc Instr. Decode Reg. Fetch Next SEQ PC Adder 4 Zero? RS 1 MUX MEM/WB Data Memory EX/MEM ALU MUX ID/EX Imm Reg File IF/ID Memory Address RS 2 Write Back MUX Next PC Memory Access WB Data Instruction Fetch Sign Extend RD RD RD • Data stationary control – local 12/3/2020 decode for each instruction phase / pipeline stage CSCE 430/830, Basic Pipelining & Performance 10

Visualizing Pipelining Figure A. 2, Page A 8 Time (clock cycles) 12/3/2020 Ifetch DMem Reg ALU O r d e r Ifetch ALU I n s t r. ALU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Reg CSCE 430/830, Basic Pipelining & Performance Reg DMem Reg 11

Instruction Level Parallelism • Review of Pipelining (the laundry analogy) 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 12

Pipelining is not quite that easy! • Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle – Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) – Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) – Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 13

One Memory Port/Structural Hazards Figure A. 4, Page A 14 Time (clock cycles) Instr 2 Instr 3 Instr 4 12/3/2020 Ifetch DMem Reg ALU Instr 1 Reg ALU Ifetch ALU O r d e r Load ALU I n s t r. ALU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Reg CSCE 430/830, Basic Pipelining & Performance Reg Reg DMem 14

One Memory Port/Structural Hazards (Similar to Figure A. 5, Page A 15) Time (clock cycles) Instr 1 Instr 2 Stall Reg Ifetch DMem Reg ALU Ifetch Bubble Instr 3 Reg DMem Bubble Ifetch Reg Bubble ALU O r d e r Load ALU I n s t r. ALU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Bubble Reg DMem How do you “bubble” the pipe? 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 15

Speed Up Equation for Pipelining For simple RISC pipeline, CPI = 1: 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 16

Example: Dual port vs. Single port • Machine A: Dual ported memory (“Harvard Architecture”) • Machine B: Single ported memory, but its pipelined implementation has a 1. 05 times faster clock rate • Ideal CPI = 1 for both • Loads are 40% of instructions executed Speed. Up. A = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe) = Pipeline Depth Speed. Up. B = Pipeline Depth/(1 + 0. 4 x 1) x (clockunpipe/(clockunpipe / 1. 05) = (Pipeline Depth/1. 4) x 1. 05 = 0. 75 x Pipeline Depth Speed. Up. A / Speed. Up. B = Pipeline Depth/(0. 75 x Pipeline Depth) = 1. 33 • Machine A is 1. 33 times faster 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 17

Data Hazard on R 1 Figure A. 6, Page A 17 Time (clock cycles) and r 6, r 1, r 7 or r 8, r 1, r 9 xor r 10, r 11 12/3/2020 Ifetch DMem Reg DMem Ifetch Reg ALU sub r 4, r 1, r 3 Reg ALU Ifetch ALU O r d e r add r 1, r 2, r 3 WB ALU I n s t r. MEM ALU IF ID/RF EX Reg CSCE 430/830, Basic Pipelining & Performance Reg Reg DMem 18 Reg

Three Generic Data Hazards • Read After Write (RAW) Instr. J tries to read operand before Instr. I writes it I: add r 1, r 2, r 3 J: sub r 4, r 1, r 3 • Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication. 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 19

Three Generic Data Hazards • Write After Read (WAR) Instr. J writes operand before Instr. I reads it I: sub r 4, r 1, r 3 J: add r 1, r 2, r 3 K: mul r 6, r 1, r 7 • Called an “anti dependence” by compiler writers. This results from reuse of the name “r 1”. • Can it happen in MIPS 5 stage pipeline? – All instructions take 5 stages, and – Reads are always in stage 2, and – Writes are always in stage 5 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 20

Three Generic Data Hazards • Write After Write (WAW) Instr. J writes operand before Instr. I writes it. I: sub r 1, r 4, r 3 J: add r 1, r 2, r 3 K: mul r 6, r 1, r 7 • Called an “output dependence” by compiler writers This also results from the reuse of name “r 1”. • Can’t happen in MIPS 5 stage pipeline because: – All instructions take 5 stages, and – Writes are always in stage 5 • Will see WAR and WAW in more complicated pipes 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 21

Forwarding to Avoid Data Hazard Figure A. 7, Page A 19 or r 8, r 1, r 9 xor r 10, r 11 12/3/2020 Reg DMem Ifetch Reg ALU and r 6, r 1, r 7 Ifetch DMem ALU sub r 4, r 1, r 3 Reg ALU O r d e r add r 1, r 2, r 3 Ifetch ALU I n s t r. ALU Time (clock cycles) Reg CSCE 430/830, Basic Pipelining & Performance Reg Reg DMem 22 Reg

HW Change for Forwarding Figure A. 23, Page A 37 Next. PC mux MEM/WR EX/MEM ALU mux ID/EX Registers Data Memory mux Immediate What circuit detects and resolves this hazard? 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 23

Forwarding to Avoid LW SW Data Hazard Figure A. 8, Page A 20 or r 8, r 6, r 9 xor r 10, r 9, r 11 Reg DMem Ifetch Reg ALU sw r 4, 12(r 1) Ifetch DMem ALU lw r 4, 0(r 1) Reg ALU O r d e r add r 1, r 2, r 3 Ifetch ALU I n s t r. ALU Time (clock cycles) Reg Reg DMem Any hazard that cannot be avoided with forwarding? 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 24 Reg

Data Hazard Even with Forwarding Figure A. 9, Page A 21 and r 6, r 1, r 7 or 12/3/2020 r 8, r 1, r 9 DMem Ifetch Reg DMem Reg Ifetch Reg CSCE 430/830, Basic Pipelining & Performance Reg DMem ALU O r d e r sub r 4, r 1, r 6 Reg ALU lw r 1, 0(r 2)Ifetch ALU I n s t r. ALU Time (clock cycles) Reg DMem 25

Data Hazard Even with Forwarding (Similar to Figure A. 10, Page A 21) and r 6, r 1, r 7 or r 8, r 1, r 9 12/3/2020 Reg DMem Ifetch Reg Bubble Ifetch Bubble Reg Bubble Ifetch Reg CSCE 430/830, Basic Pipelining & Performance How is this detected? DMem Reg Reg DMem ALU sub r 4, r 1, r 6 Ifetch ALU O r d e r lw r 1, 0(r 2) ALU I n s t r. ALU Time (clock cycles) DMem 26

Software Scheduling to Avoid Load Hazards Try producing fast code for a = b + c; d = e – f; assuming a, b, c, d , e, and f in memory. Slow code: LW LW ADD SW LW LW SUB SW Rb, b Rc, c Ra, Rb, Rc a, Ra Re, e Rf, f Rd, Re, Rf d, Rd Fast code: LW LW LW ADD LW SW SUB SW Rb, b Rc, c Re, e Ra, Rb, Rc Rf, f a, Ra Rd, Re, Rf d, Rd Compiler optimizes for performance. Hardware checks for safety. 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 27

Outline • • Review Quantify and summarize performance – Ratios, Geometric Mean, Multiplicative Standard Deviation • • F&P: Benchmarks age, disks fail, 1 point fail danger MIPS – An ISA for Pipelining 5 stage pipelining Structural and Data Hazards Forwarding Branch Schemes Exceptions and Interrupts Conclusion 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 28

r 6, r 1, r 7 22: add r 8, r 1, r 9 Reg DMem Ifetch Reg ALU 18: or Ifetch DMem ALU 14: and r 2, r 3, r 5 Reg ALU Ifetch ALU 10: beq r 1, r 3, 36 ALU Control Hazard on Branches Three Stage Stall 36: xor r 10, r 11 Reg Reg DMem What do you do with the 3 instructions in between? How do you do it? Where is the “commit”? 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 29 Reg

Branch Stall Impact • If CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1. 9! • Two part solution: – Determine branch outcome sooner, AND – Compute taken branch (target) address earlier • MIPS branch tests if register = 0 or 0 • MIPS Solution: – Move Zero test to ID/RF stage – Adder to calculate new PC in ID/RF stage – 1 clock cycle penalty for branch versus 3 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 30

Pipelined MIPS Datapath Figure A. 24, page A 38 Instruction Fetch Memory Access Write Back Adder MUX Next SEQ PC Next PC Zero? RS 1 MUX MEM/WB Data Memory EX/MEM ALU MUX ID/EX Imm Reg File IF/ID Memory Address RS 2 WB Data 4 Execute Addr. Calc Instr. Decode Reg. Fetch Sign Extend RD RD RD • Interplay of instruction set design and cycle time. 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 31

Four Branch Hazard Alternatives #1: Stall until branch direction is clear #2: Predict Branch Not Taken – – – Execute successor instructions in sequence “Squash” instructions in pipeline if branch actually taken Advantage of late pipeline state update 47% MIPS branches not taken on average PC+4 already calculated, so use it to get next instruction #3: Predict Branch Taken – 53% MIPS branches taken on average – But haven’t calculated branch target address in MIPS » MIPS still incurs 1 cycle branch penalty » Other machines: branch target known before outcome 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 32

Four Branch Hazard Alternatives #4: Delayed Branch – Define branch to take place AFTER a following instruction branch instruction sequential successor 1 sequential successor 2. . . . sequential successorn branch target if taken Branch delay of length n – 1 slot delay allows proper decision and branch target address in 5 stage pipeline – MIPS uses this 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 33

Scheduling Branch Delay Slots (Fig A. 14) A. From before branch add $1, $2, $3 if $2=0 then delay slot becomes B. From branch target sub $4, $5, $6 add $1, $2, $3 if $1=0 then delay slot becomes if $2=0 then add $1, $2, $3 C. From fall through add $1, $2, $3 if $1=0 then delay slot sub $4, $5, $6 becomes add $1, $2, $3 if $1=0 then sub $4, $5, $6 • A is the best choice, fills delay slot • In B, the sub instruction may need to be copied, increasing IC • In B and C, must be okay to execute sub when branch fails 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 34

Delayed Branch • Compiler effectiveness for single branch delay slot: – Fills about 60% of branch delay slots – About 80% of instructions executed in branch delay slots useful in computation – About 50% (60% x 80%) of slots usefully filled • Delayed Branch downside: As processor go to deeper pipelines and multiple issue, the branch delay grows and need more than one delay slot – Delayed branching has lost popularity compared to more expensive but more flexible dynamic approaches – Growth in available transistors has made dynamic approaches relatively cheaper 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 35

Evaluating Branch Alternatives Assume 4% unconditional branch, 6% conditional branch untaken, 10% conditional branch taken Scheduling Branch CPI speedup v. scheme penalty unpipelined stall Stall pipeline 3 1. 60 3. 1 1. 0 Predict taken 1 1. 20 4. 2 1. 33 Predict not taken 1 1. 14 4. 4 1. 40 Delayed branch 0. 5 1. 10 4. 5 1. 45 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 36

More branch evaluations • Suppose the branch frequencies (as percentage of all instructions) of 15% cond. Branches, 1% jumps and calls, and 60% cond. Branches are taken. Consider a 4 stage pipeline where branch is resolved at the end of the 2 nd cycle for uncond. Branches and at the end of the 3 rd cycle for cond. Branches. How much faster would the machine be without any branch hazards, ignoring other pipeline stalls? Pipeline speedupideal = Pipeline depth/(1+Pipeline stalls) = 4/(1+0) = 4 Pipeline stallsreal = (1 x 1%) + (2 x 9%) + (1 x 6%) = 0. 24 Pipeline speedupreal = 4/(1+0. 24) = 3. 23 Pipeline speedupwithout control hazards = 4/3. 23 = 1. 24 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 37

More branch question • A reduced hardware implementation of the classic 5 stage RISC pipeline might use the EX stage hardware to perform a branch instruction comparison and then not actually deliver the branch target PC to the IF stage until the clock cycle in which the branch reaches the MEM stage. Control hazard stalls can be reduced by resolving branch instructions in ID, but improving performance in one aspect may reduce performance in other circumstances. • How does determining branch outcome in the ID stage have the potential to increase data hazard stall cycles? 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 38

Problems with Pipelining • Exception: An unusual event happens to an instruction during its execution – Examples: divide by zero, undefined opcode • Interrupt: Hardware signal to switch the processor to a new instruction stream – Example: a sound card interrupts when it needs more audio output samples (an audio “click” happens if it is left waiting) • Problem: It must appear that the exception or interrupt must appear between 2 instructions (Ii and Ii+1) – The effect of all instructions up to and including Ii is totally complete – No effect of any instruction after Ii can take place • The interrupt (exception) handler either aborts program or restarts at instruction Ii+1 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 39

Precise Exceptions in Static Pipelines Key observation: architected state only change in memory and register write stages. 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 40

And In Conclusion: Control and Pipelining • Quantify and summarize performance – Ratios, Geometric Mean, Multiplicative Standard Deviation • • • F&P: Benchmarks age, disks fail, 1 point fail danger Next time: Read Appendix A, record bugs online! Control VIA State Machines and Microprogramming Just overlap tasks; easy if tasks are independent Speed Up Pipeline Depth; if ideal CPI is 1, then: • Hazards limit performance on computers: – Structural: need more HW resources – Data (RAW, WAR, WAW): need forwarding, compiler scheduling – Control: delayed branch, prediction • Exceptions, Interrupts add complexity • Next time: Read Appendix C, record bugs online! 12/3/2020 CSCE 430/830, Basic Pipelining & Performance 41