CSCE 211 Digital Logic Design ChinTser Huang huangctcse

CSCE 211: Digital Logic Design Chin-Tser Huang huangct@cse. sc. edu University of South Carolina

Chapter 5: Designing Combinational Systems

Iterative System n n A system implemented with multiple copies of a smaller circuit Consider 4 -bit adder as an example 10/09/2012 3

Delay in Combinational Logic Circuits n n When the input to a gate changes, the output of that gate will not change instantaneously Instead, there is a small delay ∆ If the output of one gate is used as the input to another gate, the delays will add The output is stable after the longest delay path 10/09/2012 4

Delay in Combinational Logic Circuits 10/09/2012 Hazard (or glitch) 5

Example of Delay 10/09/2012 6

Cascading 4 -bit Adders n Can cascade multiple 4 -bit adders if larger adders are needed 10/09/2012 7

Binary Decoder n n A binary decoder is a device that, when activated, selects one of several output lines, based on a coded input signal The input is an n-bit binary number, and there are 2 n output lines Some decoders also have one or more enable inputs Decoders are often used to select one of many devices 10/09/2012 8

Active High Decoder 10/09/2012 9

Active Low Decoder 10/09/2012 10

Decoder with Enable 10/09/2012 11

74138 Decoder 10/09/2012 12

74138 Decoder 10/09/2012 13

Use 4 3 -to-8 Decoders to Select from 32 Devices 10/09/2012 14

Use Decoder to Enable Another Decoder 10/09/2012 15

Multiplexers n n A multiplexer is a switch that passes one of its data inputs through to the output, as a function of a set of select inputs Sets of multiplexers are often used to choose among several multibit input numbers 10/09/2012 16

Two-way Multiplexer out = w if S = 0; out = x if S = 1 10/09/2012 17

Four-way Multiplexer 10/09/2012 18

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Three-variable Function Implemented with Multiplexer 10/09/2012 20

Gate Arrays n n n Also known as programmable logic device (PLD) or field programmable gate array (FPGA) An efficient way of implementing complicated systems Can implement SOP expressions which are sums of some common product terms 10/09/2012 21

Structure of a Gate Array 10/09/2012 22

An Example of Gate Array f = a’b’ + abc g = a’b’c’ + ab + bc h = a’b’ + c 10/09/2012 23

Three Types of Combinational Logic Arrays n Programmable Logic Array (PLA) n n Read-Only Memory (ROM) n n n User specifies all of the connections in both the AND array and the OR array The AND array is fixed – like a decoder consisting of 2 n AND gates for n inputs User specifies the connections in the OR array Programmable Array Logic (PAL) n The connections to the OR gates are specified; user determines the AND gate inputs 10/09/2012 24

Design with Read-Only Memories Only need a list of minterms for each function. For example, W(A, B, C, D) = ∑m(3, 7, 8, 9, 11, 15) X(A, B, C, D) = ∑m(3, 4, 5, 7, 10, 14, 15) Y(A, B, C, D) = ∑m(1, 5, 7, 11, 15) 10/09/2012 25

Structure of a PAL 10/09/2012 26