CS APP Chapter 4 Computer Architecture Processor Architecture

CS: APP Chapter 4 Computer Architecture Processor Architecture Randal E. Bryant adapted by Jason Fritts then by David Ferry http: //csapp. cs. cmu. edu CS: APP 2 e

Rest of this course: Implementing the Fetch-Decode-Execute Cycle Fetch next instruction to be executed from memory Fetch l Program counter (PC) holds the address of the next instruction to be executed Decode n Decode instruction, and send control signals to parts of datapath Execute Decode l Identify what instruction to execute l Identify what registers to read/write l Identify what immediates to use n Read register values from register file Execute n n n – 2– Perform specified operation on the data Save results in register or memory Update the PC CS: APP 2 e

Hardware Architecture - using Y 86 ISA For learning aspects of hardware architecture design, we’ll be using the Y 86 ISA n x 86 is a CISC language l too complex for educational purposes Y 86 Instruction Set Architecture n n a pseudo-language based on x 86 (IA-32) similar state, but simpler set of instructions simpler instruction formats and addressing modes more RISC-like ISA than IA-32 Format n 1– 6 bytes of information read from memory l can determine instruction length from first byte – 3– CS: APP 2 e

Y 86 Instruction Set and Formatting Byte 0 halt 0 0 nop 1 0 rrmovl r. A, r. B 2 0 r. A r. B irmovl V, r. B 3 0 F r. B V rmmovl r. A, D(r. B) 4 0 r. A r. B D mrmovl D(r. B), r. A 5 0 r. A r. B D OPl r. A, r. B 6 fn r. A r. B j. XX Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl r. A A 0 r. A F popl r. A – 6– B 0 r. A F 1 2 3 4 5 CS: APP 2 e

Y 86 Processor State RF: Program registers n %eax %esi %ecx %edx %ebx %edi %esp %ebp CC: Condition codes Stat: Program status ZF SF OF DMEM: Memory PC Program Registers l Same 8 as with IA 32. Each 32 bits n Condition Codes l Single-bit flags set by arithmetic or logical instructions » ZF: Zero n SF: Negative OF: Overflow Program Counter l Indicates address of next instruction n Program Status l Indicates either normal operation or some error condition n Memory l Byte-addressable storage array – 7– l Words stored in little-endian byte order CS: APP 2 e

Encoding Registers Each register has 4 -bit ID %eax %ecx %edx %ebx n 0 1 2 3 %esi %edi %esp %ebp 6 7 4 5 Same encoding as in IA 32 Register ID 15 (0 x. F) indicates “no register” n – 8– Will use this in our hardware design in multiple places CS: APP 2 e

Instruction Example Addition Instruction Generic Form Encoded Representation addl r. A, r. B n 6 0 r. A r. B Add value in register r. A to that in register r. B l Store result in register r. B l Note that Y 86 only allows addition to be applied to register data n Set condition codes based on result e. g. , addl %ebx, %esi Encoding: 60 36 n Two-byte encoding n l First indicates instruction type l Second gives source and destination registers – 9– CS: APP 2 e

Arithmetic and Logical Operations Instruction Code Add addl r. A, r. B Function Code 6 0 r. A r. B n Refer to generically as “OPl” n Encodings differ only by “function code” Subtract (r. A from r. B) subl r. A, r. B l Low-order 4 bytes in first instruction word 6 1 r. A r. B n And andl r. A, r. B Set condition codes as side effect 6 2 r. A r. B Exclusive-Or xorl r. A, r. B – 10 – 6 3 r. A r. B CS: APP 2 e

Y 86 Instruction Set #2 Byte 0 halt 0 0 addl 6 0 nop 1 0 subl 6 1 rrmovl r. A, r. B 2 0 r. A r. B andl 6 2 irmovl V, r. B 3 0 F r. B V xorl 6 3 rmmovl r. A, D(r. B) 4 0 r. A r. B D mrmovl D(r. B), r. A 5 0 r. A r. B D OPl r. A, r. B 6 fn r. A r. B j. XX Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl r. A A 0 r. A F popl r. A – 11 – B 0 r. A F 1 2 3 4 5 CS: APP 2 e

Move Operations rrmovl r. A, r. B irmovl V, r. B Register --> Register 2 0 r. A r. B 3 0 F r. B V rmmovl r. A, D(r. B) 4 0 r. A r. B D mrmovl D(r. B), r. A D – 12 – 5 0 r. A r. B Immediate --> Register --> Memory --> Register n Like the IA 32 movl instruction n Simpler format for memory addresses n Give different names to keep them distinct CS: APP 2 e

Move Instruction Examples IA 32 Y 86 Encoding movl $0 xabcd, %edx irmovl $0 xabcd, %edx 30 f 2 cd ab 00 00 movl %esp, %ebx rrmovl %esp, %ebx 20 43 movl -12(%ebp), %ecx mrmovl -12(%ebp), %ecx 50 15 f 4 ff ff ff movl %esi, 0 x 41 c(%esp) rmmovl %esi, 0 x 41 c(%esp) 40 64 1 c 04 00 00 movl $0 xabcd, (%eax) — movl %eax, 12(%eax, %edx) — movl (%ebp, %eax, 4), %ecx — – 14 – CS: APP 2 e

Jump Instructions Jump Unconditionally jmp Dest 7 0 Dest n Refer to generically as “j. XX” Dest n Encodings differ only by “function code” Based on values of condition codes Same as IA 32 counterparts Encode full destination address Jump When Less or Equal jle Dest 7 1 Jump When Less jl Dest 7 2 Dest Jump When Equal je Dest 7 3 n Dest Jump When Not Equal jne Dest 7 4 Dest 7 5 n l Unlike PC-relative addressing seen in IA 32 Jump When Greater or Equal jge Dest n Dest Jump When Greater jg Dest – 16 – 7 6 Dest CS: APP 2 e

Y 86 Instruction Set #3 Byte 0 halt 0 0 nop 1 0 rrmovl r. A, r. B 2 0 r. A r. B irmovl V, r. B 3 0 F r. B V rmmovl r. A, D(r. B) 4 0 r. A r. B D mrmovl D(r. B), r. A OPl r. A, r. B j. XX Dest call Dest ret pushl r. A popl r. A – 17 – 5 1 2 3 0 r. A r. B 4 5 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6 D 6 fn r. A r. B 7 fn 8 9 A B 0 Dest 0 0 r. A F CS: APP 2 e

Stack Operations pushl r. A n Decrement %esp by 4 Store word from r. A to memory at %esp n Like IA 32 n popl r. A – 18 – A 0 r. A F B 0 r. A F n Read word from memory at %esp n n Save in r. A Increment %esp by 4 n Like IA 32 CS: APP 2 e

Y 86 Program Stack “Bottom” n Region of memory holding program data n Used in Y 86 (and IA 32) for supporting procedure calls Stack top indicated by %esp n • Increasing Addresses l Address of top stack element • n • l Top element is at highest %esp Stack “Top” – 19 – Stack grows toward lower addresses address in the stack l When pushing, must first decrement stack pointer l After popping, increment stack pointer CS: APP 2 e

Subroutine Call and Return call Dest n Push address of next instruction onto stack Start executing instructions at Dest n Like IA 32 n ret 9 0 n Pop value from stack Use as address for next instruction n Like IA 32 n – 20 – 8 0 CS: APP 2 e

Miscellaneous Instructions nop n 1 0 Don’t do anything halt n n n – 21 – 0 0 Stop executing instructions IA 32 has comparable instruction, but can’t execute it in user mode Encoding ensures that program hitting memory initialized to zero will halt CS: APP 2 e

Status Conditions Mnemonic Code AOK 1 Mnemonic Code HLT 2 Mnemonic Code ADR 3 Mnemonic Code INS 4 n Normal operation n Halt instruction encountered n Bad address (either instruction or data) encountered n Invalid instruction encountered Desired Behavior n n – 22 – If AOK, keep going Otherwise, stop program execution CS: APP 2 e

Y 86 Code vs X 86 Code Coding Example n Find number of elements in null-terminated list int len 1(int a[]); a 5043 6125 7395 3 0 – 23 – CS: APP 2 e

Y 86 Code Generation Example First Try n Write typical array code Problem n Hard to do array indexing on Y 86 l Since don’t have scaled /* Find number of elements in null-terminated list */ int len 1(int a[]) { int len; for (len = 0; a[len]; len++) ; return len; } – 24 – addressing modes L 5: incl %eax cmpl $0, (%edx, %eax, 4) jne L 5 CS: APP 2 e

Y 86 Code Generation Example #2 Second Try n Write with pointer code /* Find number of elements in null-terminated list */ int len 2(int a[]) { int len = 0; while (*a++) len++; return len; } – 25 – Result n Don’t need to do indexed addressing . L 11: incl movl addl testl jne. L 11 %ecx (%edx), %eax $4, %edx %eax, %eax CS: APP 2 e

Y 86 Code Generation Example #3 IA 32 Code n Setup len 2: pushl %ebp movl %esp, %ebp movl 8(%ebp), %edx movl $0, %ecx movl (%edx), %eax addl $4, %edx testl %eax, %eax je. L 13 – 26 – Y 86 Code n Setup len 2: pushl %ebp # Save %ebp rrmovl %esp, %ebp # New FP pushl %esi # Save irmovl $4, %esi # Constant 4 pushl %edi # Save irmovl $1, %edi # Constant 1 mrmovl 8(%ebp), %edx # Get a irmovl $0, %ecx # len = 0 mrmovl (%edx), %eax# Get *a addl %esi, %edx # a++ andl %eax, %eax # Test *a je Done # If zero, goto Done n Need constants 1 & 4 n Store in callee-save registers n Use andl to test register CS: APP 2 e

Y 86 Code Generation Example #4 IA 32 Code n Loop & Exit Y 86 Code n Loop & Exit . L 11: incl %ecx movl (%edx), %eax addl $4, %edx testl %eax, %eax jne. L 11 Loop: addl %edi, %ecx # len++ mrmovl (%edx), %eax# Get *a addl %esi, %edx # a++ andl %eax, %eax # Test *a jne Loop # If !0, goto Loop . L 13: movl %ecx, %eax Done: rrmovl %ecx, popl %edi popl %esi rrmovl %ebp, popl %ebp ret leave ret – 27 – %eax # return len # Restore %edi # Restore %esi %esp # Restore SP # Restore FP CS: APP 2 e

Y 86 Code Generation Example #5 IA 32 Code n Finish . L 13: movl %ecx, %eax leave ret – 28 – Y 86 Code n Finish Done: rrmovl %ecx, popl %edi popl %esi rrmovl %ebp, popl %ebp ret %eax # return len # Restore %edi # Restore %esi %esp # Restore SP # Restore FP CS: APP 2 e

Summary Y 86 Instruction Set Architecture n Similar state and instructions as IA 32 n Simpler encodings Somewhere between CISC and RISC n How Important is ISA Design? n Less now than before l With enough hardware, can make almost anything go fast n Intel has evolved from IA 32 to x 86 -64 l Uses 64 -bit words (including addresses) l Adopted some features found in RISC » More registers (16) » Less reliance on stack – 37 – CS: APP 2 e