CS 7810 Lecture 15 A Case for ThermalAware

CS 7810 Lecture 15 A Case for Thermal-Aware Floorplanning at the Microarchitectural Level K. Sankaranarayanan, S. Velusamy, M. Stan, K. Skadron Journal of ILP, October 2005

Importance of Temperature • High power density cooling tech must improve Every additional watt increases chip’s cooling/packaging cost by $4 • Higher temperature exponentially higher leakage • Temperature variations cause wear and tear

General Approaches • Reduce overall power consumption • Wait for some unit to reach temperature limit and then throttle back (dynamic thermal management) • Better floorplans so that heat is evenly distributed and likelihood of local hotspot is reduced Better floorplanning does not eliminate the need for DTM

Thermal Modeling • Thermal resistance: models the rate at which heat passes through • Thermal capacity: models the temperature rise because of heat absorption Resistance a thickness / area Capacitance a thickness x area

Models for Alpha-like Processor

Effect of Lateral Spreading Thermal resistance = 0 Thermal resistance = infinity

Simulation Setup • Ambient temperature of 40 o C • Trigger threshold (when DTM is invoked) 111. 8 o C • Emergency threshold is 115 o C • Alpha core is 6. 2 mm x 6. 2 mm – cross-core latency is 4. 21 and 7. 16 cyc (on different metal layers) • L 2 cache is wrapped around the core to form a square

Simulated Annealing • In each iteration, perturb the solution with a probability that equals the difference between the “quality” of current and optimal solution • What is the metric for “quality”? ( A + l. W ) T W = S cij dij A is area – some layouts increase the amount of white space W is the performance penalty becoz of wire delays T is peak temperature for the layout d is the distance between units in cyc c reflects the performance impact of that distance

Inputs to Algorithm • Profile a subset of benchmarks to estimate power density of each block • Profile the performance impact of each set of wire delays to determine weights

Wire Delay Penalties

Optimal Floorplans Flp-basic each wire delay gets an equal weight Dead space 1. 14% 5. 24% Total wire length is longer here Flp-advanced wire delays are weighted

Impact on Peak Temperature Additional temp. reduction becoz of poorer IPC and lower leakage

Comparison with DTM (DVS) DVS: Assumes 10 ms overhead for a change DVS-i: Assumes no overhead for a change Emergency threshold

Title • Bullet