CS 61 C Great Ideas in Computer Architecture

CS 61 C: Great Ideas in Computer Architecture Single Cycle MIPS CPU—Part II Instructors: Krste Asanovic, Randy H. Katz http: //inst. eecs. Berkeley. edu/~cs 61 c/fa 12 10/26/2020 Fall 2012 -- Lecture #26 1

You are Here! Software • Parallel Requests Assigned to computer e. g. , Search “Katz” • Parallel Threads Assigned to core e. g. , Lookup, Ads Hardware Harness Parallelism & Achieve High Performance Smart Phone Warehouse Scale Computer • Parallel Instructions >1 instruction @ one time e. g. , 5 pipelined instructions • Parallel Data >1 data item @ one time e. g. , Add of 4 pairs of words • Hardware descriptions All gates @ one time • Programming Languages 10/26/2020 … Core Memory Core (Cache) Input/Output Instruction Unit(s) Core Functional Unit(s) A 0+B 0 A 1+B 1 A 2+B 2 A 3+B 3 Cache Memory Today Logic Gates Fall 2012 -- Lecture #26 2

Levels of Representation/Interpretation High Level Language Program (e. g. , C) Compiler Assembly Language Program (e. g. , MIPS) Assembler Machine Language Program (MIPS) temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw lw sw sw 0000 1010 1100 0101 $t 0, 0($2) $t 1, 4($2) $t 1, 0($2) $t 0, 4($2) 1001 1111 0110 1000 1100 0101 1010 0000 Anything can be represented as a number, i. e. , data or instructions 0110 1000 1111 1001 1010 0000 0101 1100 1111 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 Machine Interpretation Hardware Architecture Description (e. g. , block diagrams) Architecture Implementation Logic Circuit Description (Circuit Schematic Diagrams) Fall 2012 -- Lecture #26 10/26/2020 3

Processor Design Process • Five steps to design a processor: Processor 1. Analyze instruction set Input datapath requirements Control Memory 2. Select set of datapath components & establish Datapath Output clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic • Formulate Logic Equations • Design Circuits 10/26/2020 Fall 2012 -- Lecture #26 4

Agenda • Datapath Control • Administrivia • Control Implementation 10/26/2020 Fall 2012 -- Lecture #26 5

Agenda • Datapath Control • Administrivia • Control Implementation 10/26/2020 Fall 2012 -- Lecture #26 6

The MIPS-lite Subset • ADDU and SUBU 31 op 6 bits – addu rd, rs, rt – subu rd, rs, rt • OR Immediate: 26 31 op 31 • BRANCH: 31 – beq rs, rt, imm 16 10/26/2020 op 6 bits 5 bits 21 rs 5 bits Fall 2012 -- Lecture #26 rd 5 bits 6 shamt 5 bits 0 funct 6 bits 0 immediate 16 bits 16 rt 5 bits 11 16 21 rs 26 rt 5 bits 26 6 bits 16 21 rs op – lw rt, rs, imm 16 – sw rt, rs, imm 16 rs 5 bits 26 – ori rt, rs, imm 16 6 bits • LOAD and STORE Word 21 0 immediate 5 bits 16 rt 5 bits 0 immediate 16 bits 7

Register Transfer Language (RTL) • RTL gives the meaning of the instructions {op , rs , rt , rd , shamt , funct} MEM[ PC ] {op , rs , rt , Imm 16} MEM[ PC ] • All start by fetching the instruction Inst Register Transfers ADDU R[rd] R[rs] + R[rt]; PC + 4 SUBU R[rd] R[rs] – R[rt]; PC + 4 ORI R[rt] R[rs] | zero_ext(Imm 16); PC + 4 LOAD R[rt] MEM[ R[rs] + sign_ext(Imm 16)]; PC + 4 STORE MEM[ R[rs] + sign_ext(Imm 16) ] R[rt]; PC + 4 BEQ 10/26/2020 if ( R[rs] == R[rt] ) then PC + 4 + (sign_ext(Imm 16) || 00) else PC + 4 Fall 2012 -- Lecture #26 8

RTL: The Add Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits add rd, rs, rt – MEM[PC] Fetch the instruction from memory – R[rd] = R[rs] + R[rt] The actual operation – PC = PC + 4 Calculate the next instruction’s address 10/26/2020 Spring 2012 -- Lecture #26 9

Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction = MEM[PC] Inst Memory – same for all instructions n. PC_sel Inst Address Adder 4 Instruction<31: 0> 00 PC Mux Adder PC Ext clk imm 16 10/26/2020 Spring 2012 -- Lecture #26 10

Single Cycle Datapath during Add 31 26 op 21 16 rs rt 11 rd 6 0 shamt funct R[rd] = R[rs] + R[rt] Reg. Wr=1 bus. W 5 5 rt 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op=x Extender clk Rs Rt Rd Imm 16 zero ALUctr=ADD Memto. Reg=0 Mem. Wr=0 32 = ALU 32 rs 0 32 32 1 Data In ALUSrc=0 Spring 2012 -- Lecture #26 <0: 15> 0 <11: 15> 1 <16: 20> rt <21: 25> rd Instruction<31: 0> instr fetch unit n. PC_sel=+4 Reg. Dst=1 clk 32 0 Wr. En Adr Data Memory 1 11

Instruction Fetch Unit at End of Add • PC = PC + 4 – Same for all instructions except: Branch and Jump Inst Memory n. PC_sel=+4 Inst Address Adder 4 00 PC Mux Adder PC Ext clk imm 16 10/26/2020 Spring 2012 -- Lecture #26 12

Single Cycle Datapath during Or Immediate 31 26 21 op 16 rs 0 rt immediate • R[rt] = R[rs] OR Zero. Ext[Imm 16] bus. W Rs Rt 5 5 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op= Extender clk 32 = ALU 32 Rs Rt Rd zero ALUctr= 0 0 32 32 1 ALUSrc= Data In Fall 2012 -- Lecture #26 clk <0: 15> Reg. Wr= <11: 15> 1 clk <16: 20> Rd Rt Instruction<31: 0> instr fetch unit <21: 25> n. PC_sel= Reg. Dst= Student Roulette Imm 16 Memto. Reg= Mem. Wr= 32 0 Wr. En Adr Data Memory 1 13

Single Cycle Datapath during Or Immediate 31 26 21 op 16 rs 0 rt immediate • R[rt] = R[rs] OR Zero. Ext[Imm 16] 5 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op=zero Extender clk 32 = ALU 32 5 Rs Rt 0 32 32 1 Data In ALUSrc=1 Fall 2012 -- Lecture #26 clk <0: 15> bus. W Rs Rt Rd zero ALUctr=OR 0 Reg. Wr=1 <11: 15> clk Rd Rt 1 instr fetch unit <21: 25> Reg. Dst=0 Instruction<31: 0> <16: 20> n. PC_sel=+4 Imm 16 Memto. Reg=0 Mem. Wr=0 32 0 Wr. En Adr Data Memory 1 14

Single Cycle Datapath during Load 31 26 21 op 16 rs 0 rt immediate • R[rt] = Data Memory {R[rs] + Sign. Ext[imm 16]} bus. W Rs Rt 5 5 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op= Extender clk 32 = ALU 32 Rs Rt Rd zero ALUctr= 0 0 32 32 1 ALUSrc= Data In Fall 2012 -- Lecture #26 clk <0: 15> Reg. Wr= <11: 15> 1 clk Instruction<31: 0> <16: 20> Rd Rt instr fetch unit <21: 25> n. PC_sel= Reg. Dst= Student Roulette Imm 16 Memto. Reg= Mem. Wr= 32 0 Wr. En Adr Data Memory 1 15

Single Cycle Datapath during Load 31 26 21 op 16 rs 0 rt immediate • R[rt] = Data Memory {R[rs] + Sign. Ext[imm 16]} 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op=sign Extender clk Rs Rt Rd Imm 16 zero ALUctr=ADD Memto. Reg=1 Mem. Wr=0 32 = ALU 32 5 0 32 32 <0: 15> bus. W 5 Rs Rt <11: 15> Reg. Wr=1 <16: 20> 0 <21: 25> Rd Rt 1 Instruction<31: 0> instr fetch unit n. PC_sel=+4 Reg. Dst=0 clk 1 Data In ALUSrc=1 Fall 2012 -- Lecture #26 clk 32 0 Wr. En Adr Data Memory 1 16

Single Cycle Datapath during Store 31 26 21 op 16 rs 0 rt immediate • Data Memory {R[rs] + Sign. Ext[imm 16]} = R[rt] bus. W Rs Rt 5 5 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op= Extender clk 32 = ALU 32 Rs Rt Rd zero ALUctr= 0 0 32 32 1 ALUSrc= Data In Fall 2012 -- Lecture #26 clk <0: 15> Reg. Wr= <11: 15> 1 clk Instruction<31: 0> <16: 20> Rd Rt instr fetch unit <21: 25> n. PC_sel= Reg. Dst= Student Roulette Imm 16 Memto. Reg= Mem. Wr= 32 0 Wr. En Adr Data Memory 1 17

Single Cycle Datapath during Store 31 26 21 op 16 rs 0 rt immediate • Data Memory {R[rs] + Sign. Ext[imm 16]} = R[rt] bus. W 5 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op=sign Extender clk Rs Rt Rd Imm 16 zero ALUctr=ADD Memto. Reg=x Mem. Wr=1 32 = ALU 32 5 Rs Rt 0 32 32 <0: 15> Reg. Wr=0 <11: 15> 0 <16: 20> Rd Rt <21: 25> n. PC_sel=+4 Reg. Dst=x clk 1 Instruction<31: 0> instr fetch unit 1 Data In ALUSrc=1 Fall 2012 -- Lecture #26 clk 32 0 Wr. En Adr Data Memory 1 18

Single Cycle Datapath during Branch 31 26 21 op • 16 rs 0 rt immediate if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 bus. W Rs Rt 5 5 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op= Extender clk 32 = ALU 32 Rs Rt Rd zero ALUctr= 0 0 32 32 1 ALUSrc= Data In Fall 2012 -- Lecture #26 clk <0: 15> Reg. Wr= <11: 15> 1 clk <16: 20> Rd Rt Instruction<31: 0> <21: 25> n. PC_sel= Reg. Dst= instr fetch unit Imm 16 Memto. Reg= Mem. Wr= 32 0 Wr. En Adr Data Memory 1 19

Single Cycle Datapath during Branch 31 26 21 op • 16 rs 0 rt immediate if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 5 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 10/26/2020 16 Ext. Op=x Extender clk Rs Rt Rd Imm 16 zero ALUctr=SUB Memto. Reg=x Mem. Wr=0 32 = ALU 32 5 0 32 32 <0: 15> bus. W Rs Rt <11: 15> Reg. Wr=0 <16: 20> 0 <21: 25> Rd Rt 1 Instruction<31: 0> instr fetch unit n. PC_sel=br Reg. Dst=x clk 1 Data In ALUSrc=0 Fall 2012 -- Lecture #26 clk 32 0 Wr. En Adr Data Memory 1 20

Instruction Fetch Unit at the End of Branch 31 26 op 21 16 rs 0 rt immediate • if (Zero == 1) then PC = PC + 4 + Sign. Ext[imm 16]*4 ; else PC = PC + 4 Inst Memory Adr n. PC_sel Zero 0 Mux PC Adder 10/26/2020 PC Ext imm 16 Adder 4 00 MUX ctrl n. PC_sel Instruction<31: 0> • What is encoding of n. PC_sel? • Direct MUX select? • Branch inst. / not branch • Let’s pick 2 nd option Q: What logic gate? 1 clk Fall 2012 -- Lecture #26 21

Summary: Datapath’s Control Signals • Ext. Op: • ALUsrc: • ALUctr: • • “zero”, “sign” 0 reg. B; 1 immed “ADD”, “SUB”, “OR” Mem. Wr: Memto. Reg: Reg. Dst: Reg. Wr: ALUctr Memto. Reg Mem. Wr Reg. Dst Rd Rt 1 Inst Address Reg. Wr 4 clk 32 Rs Rt 5 5 5 Rw Ra Rb bus. A Reg. File bus. B 32 clk imm 16 16 Ext. Op Extender imm 16 PC Mux Adder PC Ext 10/26/2020 1 bus. W 0 32 0 ALU Adder 0 00 n. PC_sel 1 write memory 0 ALU; 1 Mem 0 “rt”; 1 “rd” 1 write register 32 0 32 Wr. En Adr 32 Fall 2012 -- Lecture #26 1 ALUSrc Data In clk 1 Data Memory 22

Agenda • Datapath Control • Administrivia • Control Implementation 10/26/2020 Fall 2012 -- Lecture #26 23

CS 61 c in the News 10/26/2020 Fall 2012 -- Lecture #26 24

10/26/2020 Fall 2012 -- Lecture #26 25

Agenda • Datapath Control • Administrivia • Control Implementation 10/26/2020 Fall 2012 -- Lecture #26 26

Given Datapath: RTL Control Instruction<31: 0> Rd <0: 15> Rs <11: 15> Rt <16: 20> Op Fun <21: 25> <0: 5> <26: 31> Inst Memory Adr Imm 16 Control n. PC_sel Reg. Wr Reg. Dst Ext. Op ALUSrc ALUctr Mem. Wr Memto. Reg DATA PATH 10/26/2020 Fall 2012 -- Lecture #26 27

Summary of the Control Signals (1/2) inst Register Transfer add R[rd] R[rs] + R[rt]; PC + 4 ALUsrc=Reg. B, ALUctr=“ADD”, Reg. Dst=rd, Reg. Wr, n. PC_sel=“+4” sub R[rd] R[rs] – R[rt]; PC + 4 ALUsrc=Reg. B, ALUctr=“SUB”, Reg. Dst=rd, Reg. Wr, n. PC_sel=“+4” R[rt] R[rs] + zero_ext(Imm 16); PC + 4 ori ALUsrc=Im, Extop=“Z”, ALUctr=“OR”, Reg. Dst=rt, Reg. Wr, n. PC_sel=“+4” R[rt] MEM[ R[rs] + sign_ext(Imm 16)]; PC + 4 lw ALUsrc=Im, Extop=“sn”, ALUctr=“ADD”, Memto. Reg, Reg. Dst=rt, Reg. Wr, n. PC_sel = “+ MEM[ R[rs] + sign_ext(Imm 16)] R[rs]; PC + 4 sw ALUsrc=Im, Extop=“sn”, ALUctr = “ADD”, Mem. Wr, n. PC_sel = “+4” beq if (R[rs] == R[rt]) then PC + sign_ext(Imm 16)] || 00 else PC + 4 n. PC_sel = “br”, ALUctr = “SUB” 10/26/2020 Fall 2012 -- Lecture #26 28

Summary of the Control Signals (2/2) See Appendix A func 10 0000 10 0010 We Don’t Care : -) op 00 0000 00 1101 10 0011 10 1011 00 0100 Reg. Dst ALUSrc Memto. Reg. Write Mem. Write n. PCsel Jump Ext. Op ALUctr<2: 0> 31 add 1 0 0 0 x Add 26 sub 1 0 0 0 x Subtract 21 lw 0 1 1 1 0 0 0 1 Add 16 R-type op rs rt I-type op rs rt 10/26/2020 ori 0 1 0 0 Or sw x 1 x 0 1 0 0 1 Add 11 rd Fall 2012 -- Lecture #26 beq x 0 0 1 0 x Subtract 6 shamt immediate 0 funct add, sub ori, lw, sw, beq 29

Boolean Expressions for Controller Reg. Dst = add + sub ALUSrc = ori + lw + sw Memto. Reg = lw Reg. Write = add + sub + ori + lw Mem. Write = sw n. PCsel = beq Jump = jump Ext. Op = lw + sw ALUctr[0] = sub + beq (assume ALUctr is 00 ADD, 01: SUB, 10: OR) ALUctr[1] = or Where: rtype = ~op 5 ~op 4 ~op 3 ~op 2 ~op 1 ~op 0, ori = ~op 5 ~op 4 op 3 op 2 ~op 1 op 0 lw = op 5 ~op 4 ~op 3 ~op 2 op 1 op 0 sw = op 5 ~op 4 op 3 ~op 2 op 1 op 0 beq = ~op 5 ~op 4 ~op 3 op 2 ~op 1 ~op 0 jump = ~op 5 ~op 4 ~op 3 ~op 2 op 1 ~op 0 add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func 1 ~func 0 sub = rtype func 5 ~func 4 ~func 3 ~func 2 func 1 ~func 0 10/26/2020 Fall 2012 -- Lecture #26 How do we implement this in gates? 30

Controller Implementation opcode func “AND” logic 10/26/2020 add sub ori lw sw beq “OR” logic Fall 2012 -- Lecture #26 Reg. Dst ALUSrc Memto. Reg. Write Mem. Write n. PCsel Ext. Op ALUctr[0] ALUctr[1] 31

AND Control in Logisim 10/26/2020 Fall 2012 -- Lecture #26 32

OR Control Logic in Logisim 10/26/2020 Fall 2012 -- Lecture #26 33

Single Cycle Performance • Assume time for actions are – 100 ps for register read or write; 200 ps for other events • Clock rate is? Instr fetch Register read ALU op Memory access Register write Total time lw 200 ps 100 ps 800 ps sw 200 ps 100 ps 200 ps R-format 200 ps 100 ps 200 ps beq 200 ps 100 ps 200 ps 700 ps 100 ps 600 ps 500 ps • What can we do to improve clock rate? • Will this improve performance as well? Want increased clock rate to mean faster programs 10/26/2020 Fall 2012 -- Lecture #26 Student Roulette? 34

And in Conclusion, … Single-Cycle Processor • Five steps to design a processor: Processor 1. Analyze instruction set Input datapath requirements Control Memory 2. Select set of datapath components & establish Datapath Output clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic • Formulate Logic Equations • Design Circuits 10/26/2020 Fall 2011 -- Lecture #26 35