CS 370 Operating Systems Operating System Structures This

CS 370: Operating Systems Operating System Structures This lecture is partially derived from online material copyright Silberschatz, Galvin and Gagne, and partially adopted from online class notes from Prof John Kubiatowicz, Copyright © 2007 UCB © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 1

Computer System Structures Computer System Operation I/O Structure Storage Hierarchy Hardware Protection General System Architecture © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 2

Architecture of a Typical Computer System © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 3

Computer System Operation I/O devices and the CPU can execute concurrently Each device controller is in charge of a particular device type Each device controller has a local buffer CPU moves data from/to main memory to/from local buffers I/O is from the device to local buffer of controller Device controller informs CPU that it has finished its operation by causing an interrupt © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 4

Common Functions of Interrupts Interrupt transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines Interrupt architecture must save the address of the interrupted instruction Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt A trap is a software-generated interrupt caused either by an error or a user request An operating system is interrupt driven © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 5

Interrupt Handling The operating system preserves the state of the CPU by storing registers and the program counter Determines which type of interrupt has occurred: n n polling vectored interrupt system Separate kernel routines determine what action should be taken for each type of interrupt © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 6

Interrupt Time Line For a Single Process Doing Output We will get to more of this later, modern devices via DMA limits the CPU involvement in managing interrupts © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 7

I/O Structure Synchronous I/O - After I/O starts, control returns to user program only upon I/O completion n Wait instruction idles the CPU until the next interrupt Wait loop (contention for memory access) At most one I/O request is outstanding at a time, no simultaneous I/O processing Asynchronous I/O - After I/O starts, control returns to user program without waiting for I/O completion n System call – request to the operating system to allow user n n to wait for I/O completion Device-status table contains entry for each I/O device indicating its type, address, and state Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 8

Synchronous versus Asynchronous Interrupt Processing © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 9

The Device Status Table © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 10

Improving Performance: Direct Memory Access (DMA) Structure Used for high-speed I/O devices able to transmit information at close to memory speeds Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention Only on interrupt is generated per block, rather than the one interrupt per byte © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 11

Storage Structure Main memory – only large storage media that the CPU can access directly Cache – Memory on the CPU that can be quickly accessed without going over the memory bus Secondary storage – extension of main memory that provides large nonvolatile storage capacity Magnetic disks – rigid metal or glass platters covered with magnetic recording material n Disk surface is logically divided into tracks, which are subdivided into sectors n The disk controller determines the logical interaction between the device and the computer Removable Storage – highly transportable read and read/write storage devices (e. g. , DVD’s, USB Disks, Flash Cards, etc. ) © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 12

Moving-Head Disk Mechanism © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 13

Changing Disk Capacity Footprint © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 14

Storage Hierarchy Faster/Smaller Slower/Bigger © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 15

Storage Hierarchy Storage systems organized in hierarchy n n n Speed Cost Volatility Caching – copying information into faster storage system; main memory can be viewed as a last cache for secondary storage © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 16

Caching Use of high-speed memory to hold recently-accessed data Requires a cache management policy Caching introduces another level in storage hierarchy. n This requires data that is simultaneously stored in more than one level to be consistent Think about issues in a multi-processor – Cache coherence… © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 17

Hardware Protection Dual-Mode Operation I/O Protection Memory Protection CPU Protection © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 18

Dual-Mode Operation Sharing system resources requires operating system to ensure that an incorrect program or poorly behaving human cannot cause other programs to execute incorrectly OS must provide hardware support to differentiate between at least two modes of operations 1. User mode – execution done on behalf of a user 2. Monitor mode (also kernel mode or system mode) – execution done on behalf of operating system © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 19

Dual-Mode Operation (Cont. ) Mode bit added to computer hardware to indicate the current mode: monitor (0) or user (1) When an interrupt or fault occurs hardware switches to monitor mode Interrupt/fault monitor user set user mode Privileged instructions can be issued only in monitor mode © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 20

I/O Protection All I/O instructions are privileged instructions Must ensure that a user program could never gain control of the computer in monitor mode (I. e. , a user program that, as part of its execution, stores a new address in the interrupt vector) © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 21

Use of A System Call to Perform I/O © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 22

Memory Protection Must provide memory protection at least for the interrupt vector and the interrupt service routines In order to have memory protection, at a minimum add two registers that determine the range of legal addresses a program may access: n n Base register – holds the smallest legal physical memory address Limit register – contains the size of the range Memory outside the defined range is protected © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 23

Use of A Base and Limit Register © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 24

Hardware Address Protection © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 25

Hardware Protection When executing in monitor mode, the operating system has unrestricted access to both monitor and user’s memory The load instructions for the base and limit registers are privileged instructions © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 26

CPU Protection Timer – interrupts computer after specified period to ensure operating system maintains control n n Timer is decremented every clock tick When timer reaches the value 0, an interrupt occurs Timer commonly used to implement time sharing Time also used to compute the current time Load-timer is a privileged instruction © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 27

General-System Architecture Given the I/O instructions are privileged, how does the user program perform I/O? System call – the method used by a process to request action by the operating system n n n Usually takes the form of a trap to a specific location in the interrupt vector Control passes through the interrupt vector to a service routine in the OS, and the mode bit is set to monitor mode The monitor verifies that the parameters are correct and legal, executes the request, and returns control to the instruction following the system call © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 28

Network Structure Local Area Networks (LAN) Wide Area Networks (WAN) © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 29

Local Area Network Structure © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 30

Wide Area Network Structure © Drexel University Software Engineering Research Group (SERG) http: //serg. cs. drexel. edu 31