CS 244 Introduction to Embedded Systems and Ubiquitous
CS 244 -Introduction to Embedded Systems and Ubiquitous Computing Instructor: Eli Bozorgzadeh Computer Science Department UC Irvine Winter 2010
CS 244 – Lecture 5 Hardware/Software Co-design Winter 2010 - CS 244 2
Review: Design Objectives Cost Improving cost is desired Better te r Performance Be t Improving quality beyond threshold is desired Improving performance beyond threshold Is a waste Thresholds Quality Winter 2010 - CS 244 3
Co-design Flow Refine Informal Specification System Model System Simulation Algorithmic Design Hardware/Software Partitioning Partitioned Model Schedule HW/SW Co-simulation Partitioned Model & Sch. Winter 2010 - CS 244 4
Co-design Flow Partitioned Model + Sch. Communication Synthesis Software Model HW/SW Co-simulation Compilation Binary Exec. Model Refine Hardware Model Synthesis HW/SW Co-simulation Winter 2010 - CS 244 Gate-level Model 5
Co-design Flow Refine Binary Exec. Model Emulate or Prototype Gate-level Model Fabrication Winter 2010 - CS 244 6
Informal Specification & System Level Model n n Informal Specification loosely defines high level behavior, constraints, and optimization objectives of the system q Algorithmic and implementation details absent q Performance estimates not present System level model formally captures behavior, constraints, and optimization objectives q Can be simulated to obtain early performance estimates n q n Feedback to refine the system specification Can serve as a golden model for validation of intermediate or final stages Algorithmic design Winter 2010 - CS 244 7
Hardware Software Partitioning n n n Decompose (i. e. , partition) the function F of the system into N sub-functions F 1, F 2, F 3 … FN Decompose the constraints and design objectives of the system into sub-constraints and design sub-objectives Cluster F 1, F 2, F 3, …, Fn into M partitions to run on M processors F {F 1, F 2, F 3 … Fn} … P 1 Winter 2010 - CS 244 P 2 P 3 … PM 8
Scheduling n n Scheduling is to obtain an execution sequence such that dependencies are obeyed Static q n F 1 F 4 During design time the schedule is fixed (the common case) F 5 F 6 Dynamic q F 2 During execution time, the schedule is determined (reconfigurable computing) F 7 F 3 P 1: F 1 F 2 F 8 P 2: F 4 F 5 P 3: F 3 F 6 P 4: F 7 Winter 2010 - CS 244 F 8 9
Scheduling n n A deadline D for the entire schedule An execution time for each Ti for each Fi ASAP (as soon as possible) ALAP (as late as possible) F 2 3 F 1 3 F 4 6 F 6 2 F 5 F 7 F 3 1 P 1: F 1 F 2 F 8 P 2: F 4 F 5 P 3: F 3 F 6 P 4: F 7 Winter 2010 - CS 244 3 F 8 3 10 4
Partitioning (Clustering) n Given: q q n n n F = { F 1, F 2, F 3 … FN } P = { P 1, P 2, P 3 … PM } Find a lowest cost partition (cluster), as computed by an objective function Exhaustive approach O(MN) Heuristics q Constructive partitioning (based on closeness function) n n n q Random (good for seeding iterative approaches) Cluster Growth Hierarchical clustering Iterative partitioning n n Start with a partition and improve Gradient search Controlled random search Modified Kernighan/Lin and FM algorithm q q q n n n Partitions a set of nodes (functions) into two bins (processors) Minimize edges between bins (communication cost, wires, etc. ) Cost function for moving a node from one partition to another ILP Genetic evolution Simulated annealing Winter 2010 - CS 244 11
Partitioning (Clustering) n Given: q q n n n F = { F 1, F 2, F 3 … FN } P = { P 1, P 2, P 3 … PM } Find a lowest cost partition (cluster), as computed by an objective function Exhaustive approach O(MN) Heuristics q Constructive partitioning (based on closeness function) n n n q Random (good for seeding iterative approaches) Cluster Growth Hierarchical clustering Iterative partitioning n n Start with a partition and improve Gradient search Controlled random search Modified Kernighan/Lin algorithm q q q n n n Partitions a set of nodes (functions) into two bins (processors) Minimize edges between bins (communication cost, wires, etc. ) Cost function for moving a node from one partition to another ILP Genetic evolution Simulated annealing Winter 2010 - CS 244 12
Iterative Partitioning Algorithms n n The computation time in an iterative algorithm is spent evaluating large numbers of partitions Iterative algorithms differ from one another primarily in the ways in which they modify the partition and in which they accept or reject bad modifications
Kernighan-Lin (Min-Cut) Algorithms n Two-way partitioning example Start with 2 equal subgraphs q Exchange k pairs in each iteration q Continue until no further improvement q n Gain function q f(internal – external) cost
Hierarchical Clustering – Example Winter 2010 - CS 244 15
Clustering w/ several criteria
Alternate Partitioning Techniques n n Start with all functionality in software and move portions into hardware which are timecritical and can not be allocated to software (software-oriented partitioning) Start with all functionality in hardware and move portions into software implementation (hardware-oriented partitioning) Winter 2010 - CS 244 17
More Partitioning Issues n n Partitioning into hardware and software affects overall system cost and performance Hardware implementation q q n Provides higher performance via hardware speeds and parallel execution of operations Incurs additional design expense Software implementation q q Lower performance Incurs high cost of developing and maintaining (complex) software Winter 2010 - CS 244 18
Functional Co-simulation n n Some of the M processors are single-purpose (e. g. , those with a single function mapped on to them), others are general purpose Functions mapped onto the general-purpose processors are implemented in software and simulated on virtual machines with performance models Functions mapped onto the single-purpose processors are simulated at the behavioral level with performance models Communication is done via abstract channels Feedback is used to refine the partitioning and scheduling tasks Winter 2010 - CS 244 19
Communication Synthesis & Busaccurate Co-simulation n n Abstract channels A 1, A 2 … An are mapped onto a set of communication channels C 1, C 2 … Cm q Similar to functional partitioning q Similar to hardware/software scheduling Channels correspond to physical artifacts of the architecture Hardware and software models are annotated with detailed communication constructs A hardware model and software model is obtained and cosimulated Communication synthesis (or possibly higher levels of design) are refined Winter 2010 - CS 244 20
Compilation & Synthesis & Cycleaccurate Co-simulation n n Compiler used to generate binary executables for general-purpose processors Synthesis used to generate gate-level models of single-purpose processors Synthesis used to generate gate-level models of general-purpose processors Cycle accurate co-simulation of the entire system q Note: mixed level co-simulation is common Winter 2010 - CS 244 21
Emulate/Prototype and Fabrication n n Use hardware (e. g, FPGAs) to emulate a system as fast as possible (relative to real-time) Fabrication q q q Place & route Mask design Chip testing n n q Manufacturing fault models Test vector generation Packaging Winter 2010 - CS 244 22
Conclusion n n Satisfying performance, cost, and quality metrics of a system entails hardware and software codesign Partitioning is at the heart of codesign q q q n Partitioning techniques q q n Functional Communication Scheduling Constructive Iterative Heuristics often used to bound the running time Winter 2010 - CS 244 23
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