CS 2422 Assembly Language and System Programming System

CS 2422 Assembly Language and System Programming System Software and Machine Architecture Department of Computer Science National Tsing Hua University

Chapter Outline Chapter 1 of Beck’s “System Software” book 1. 1 Introduction 1. 2 System Software and Machine Architecture 1. 3 Simplified Instructional Computer (SIC) l l l SIC Machine Architecture SIC/XE Machine Architecture SIC Programming Examples 1

System Software u System software consists of a variety of programs that support the operation of a computer, e. g. l Text editor, compiler, loader or linker, debugger, macro processors, operating system, database management systems, software engineering tools, …. 2

System Software & Architecture u System software differs from application software in machine dependency l u u System programs are intended to support the operation and use of the computer itself, rather than any particular application. Thus, we must include real machines and real pieces of software in our study Simplified Instructional Computer (SIC) l SIC is a hypothetical computer that includes the hardware features most often found on real machines, while avoiding unusual or irrelevant complexities 3

Simplified Instructional Computer u Like many other products, SIC comes in two versions l l The standard model An XE version ‒ “extra equipments”, “extra expensive” u The two versions have been designed to be upward compatible 4

SIC Machine Architecture (1/5) u Memory l l l u Memory consists of 8 -bit bytes, 15 -bit addresses Any 3 consecutive bytes form a word (24 bits) Total of 32768 (215) bytes in the computer memory Registers l Five registers, each is 24 bits in length Mnemonic Number Special use A 0 Accumulator X 1 Index register L 2 Linkage register PC 8 Program counter SW 9 Status word 5

SIC Machine Architecture (2/5) u Data formats l l l u 24 -bit integer representation in 2’s complement 8 -bit ASCII code for characters No floating-point on standard version of SIC Instruction formats l l Standard version of SIC 8 1 15 opcode x address The flag bit x is used to indicate indexedaddressing mode 6

SIC Machine Architecture (3/5) u Addressing modes l Two addressing modes ‒ Indicated by the x bit in the instruction Mode Indication Target address calculation Direct x=0 TA=address Indexed x=1 TA=address+(X) (X): the contents of register X 7

SIC Machine Architecture (4/5) Instruction set: (Appendix A, Page 495) u Load/store registers: LDA, LDX, STA, STX u Integer arithmetic: ADD, SUB, MUL, DIV l u COMP l l u All involve register A and a word in memory, result stored in register A Compare value in register A with a word in memory Set a condition code CC (<, =, or >) Conditional jump instructions l JLT, JEQ, JGT: test CC and jump 8

SIC Machine Architecture (5/5) u Subroutine linkage l u JSUB, RSUB: return address in register L Input and output l l Performed by transferring 1 byte at a time to or from the rightmost 8 bits of register A Each device is assigned a unique 8 -bit code, as an operand of I/O instructions Test Device (TD): < (ready), = (not ready) Read Data (RD), Write Data (WD) 9

SIC Programming Example (Fig 1. 2 a) u Data movement ALPHA FIVE CHARZ C 1 LDA STA LDCH STCH. . . RESW WORD BYTE RESB FIVE ALPHA CHARZ C 1 load 5 into A store in ALPHA load ‘Z’ into A store in C 1 1 5 C’Z’ 1 reserve one word space one word holding 5 one-byte constant one-byte variable 10

SIC Programming Example (Fig 1. 3 a) u Arithmetic operations: BETA = ALPHA+INCR-1 ONE ALPHA BETA GAMMA DELTA INCR LDA ADD SUB STA. . . WORD RESW RESW ALPHA INCR ONE BETA GAMMA INCR ONE DELTA 1 1 1 one-word constant one-word variables 11

SIC Programming Example (Fig 1. 4 a) u Looping and indexing: copy one string to another LDX MOVECH LDCH STCH TIX JLT. . . STR 1 BYTE STR 2 RESB ZERO WORD ELEVEN WORD ZERO STR 1, X STR 2, X ELEVEN MOVECH initialize index register to 0 load char from STR 1 to reg A add 1 to index, compare to 11 loop if “less than” C’TEST STRING’ 11 0 11 12

SIC Programming Example (Fig 1. 5 a) ADDLP INDEX ALPHA BETA GAMMA ZERO THREE K 300 LDA STA LDX LDA ADD STA COMP JLT. . . RESW WORD ZERO INDEX ALPHA, X BETA, X GAMMA, X INDEX THREE INDEX K 300 ADDLP 1 100 100 0 3 300 initialize index value to 0 load index value to reg X load word from ALPHA into reg A store the result in a word in GAMMA add 3 to index value compare new index value to 300 loop if less than 300 array variables— 100 words each one-word constants 13

SIC Programming Example (Fig 1. 6) u Input and output INLOOP TD JEQ RD STCH. . OUTLP TD JEQ LDCH WD. . INDEV BYTE OUTDEV BYTE DATA RESB INDEV INLOOP INDEV DATA test input device loop until device is ready read one byte into register A OUTDEV OUTLP DATA OUTDEV test output device loop until device is ready X’F 1’ X’ 05’ 1 input device number output device number write one byte to output device 14

SIC/XE Machine Architecture (1/11) u Memory l l l Maximum memory available on a SIC/XE system is 1 megabyte (220 bytes) An address (20 bits) cannot be fitted into a 15 -bit field as in SIC Standard Must change instruction formats and addressing modes 15

SIC/XE Machine Architecture (2/11) u Registers l Additional registers are provided by SIC/XE Mnemonic Number Special use B 3 Base register S 4 General working register T 5 General working register F 6 Floating-point accumulator (48 bits) 16

SIC/XE Machine Architecture (3/11) u There is a 48 -bit floating-point data type l l l fraction is a value between 0 and 1 exponent is an unsigned binary number between 0 and 2047 zero is represented as all 0 1 11 36 s exponent fraction f*2(e-1024) 17

SIC/XE Machine Architecture (4/11) u Instruction formats 8 Format 1 (1 byte) op Format 2 (2 bytes) Format 3 (3 bytes) Format 4 (4 bytes) 8 4 4 op r 1 r 2 6 1 1 1 12 op n i x b p e disp 6 1 1 1 20 op n i x b p e address Formats 1 and 2 do not reference memory at all Bit e distinguishes between format 3 and 4 18

SIC/XE Machine Architecture (5/11) u Base Relative Addressing Mode n i x b p e opcode 1 0 disp (0 disp 4095) b=1, p=0, TA=(B)+disp u Program-Counter Relative Addressing Mode n i x b p e opcode 0 1 b=0, p=1, TA=(PC)+disp (-2048 disp 2047) 19

SIC/XE Machine Architecture (6/11) u Direct Addressing Mode n i x b p e opcode 0 0 b=0, p=0, TA=disp (0 disp 4095) n i x b p e opcode 1 0 0 disp b=0, p=0, TA=(X)+disp (with index addressing mode) 20

SIC/XE Machine Architecture (7/11) u Immediate Addressing Mode n i x b p e opcode 0 1 0 disp n=0, i=1, x=0, operand=disp u Indirect Addressing Mode n i x b p e opcode 1 0 0 disp n=1, i=0, x=0, TA=(disp) 21

SIC/XE Machine Architecture (8/11) u Simple Addressing Mode n i x b p e opcode 0 0 disp i=0, n=0, TA=bpe+disp (SIC standard) opcode+n+i = SIC standard opcode (8 -bit) n i x b p e opcode 1 1 disp i=1, n=1, TA=disp (SIC/XE standard) 22

SIC/XE Machine Architecture (9/11) u Addressing Modes Summary (p. 499) Assembler decides which format to use 23

SIC/XE Machine Architecture (10/11) Example Instruction Format (PC) + disp (B) + disp + (X) ((PC) + disp) disp b/p/e + disp addr 24

SIC/XE Machine Architecture (11/11) u Instruction set: l l load and store the new registers: LDB, STB, etc. Floating-point arithmetic operations ‒ ADDF, SUBF, MULF, DIVF l l Register move: RMO Register-to-register arithmetic operations ‒ ADDR, SUBR, MULR, DIVR l u Supervisor call: SVC Input and output: l I/O channels to perform I/O while CPU is executing other instructions: SIO, TIO, HIO 25

SIC/XE Programming Example SIC version (Fig 1. 2 b) FIVE ALPHA CHARZ C 1 ALPHA LDA STA LDCH STCH. . . RESW 1 SIC/XE version LDA #5 STA ALPHA LDCH #90 STCH C 1. . . ALPHA RESW 1 FIVE WORD 5 C 1 CHARZ BYTE C’Z’ C 1 RESB 1 26

SIC/XE Programming Example ALPHA BETA GAMMA DELTA INCR LDS LDA ADDR SUB STA. . . RESW RESW INCR ALPHA S, A #1 BETA GAMMA S, A #1 DELTA 1 1 1 (Fig 1. 3 b) BETA=ALPHA+INCR-1 DELTA=GAMMA+INCR-1 one-word variables 27

SIC/XE Programming Example u (Fig 1. 4 b) Looping and indexing: copy one string to another LDT LDX MOVECH LDCH STCH TIXR JLT. . . STR 1 BYTE STR 2 RESB #11 #0 STR 1, X STR 2, X T MOVECH initialize register T to 11 initialize index register to 0 load char from STR 1 to reg A store char into STR 2 add 1 to index, compare to 11 loop if “less than” 11 C’TEST STRING’ 11 28

SIC/XE Programming Example ADDLP ALPHA BETA GAMMA LDS LDT LDX LDA ADD STA ADDR COMPR JLT. . . RESW #3 #300 #0 ALPHA, X BETA, X GAMMA, X S, X X, T ADDLP 100 100 (Fig 1. 5 b) load from ALPHA to reg A store in a word in GAMMA add 3 to index value compare to 300 loop if less than 300 array variables— 100 words each 29

SIC/XE Programming Example (Fig 1. 7 b) 30