CS 162 Operating Systems and Systems Programming Lecture

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CS 162 Operating Systems and Systems Programming Lecture 9 Address Translation February 24, 2014

CS 162 Operating Systems and Systems Programming Lecture 9 Address Translation February 24, 2014 Anthony D. Joseph http: //inst. eecs. berkeley. edu/~cs 162

Goals for Today • Address Translation Schemes – Segmentation – Paging – Multi-level translation

Goals for Today • Address Translation Schemes – Segmentation – Paging – Multi-level translation – Paged page tables – Inverted page tables Note: Some slides and/or pictures in the following are adapted from slides © 2005 Silberschatz, Galvin, and Gagne. Slides courtesy of Anthony D. Joseph, John Kubiatowicz, AJ Shankar, George Necula, Alex Aiken, Eric Brewer, Ras Bodik, Ion Stoica, Doug Tygar, and David Wagner. 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 2

Virtualizing Resources • Physical Reality: Processes/Threads share the same hardware – Need to multiplex

Virtualizing Resources • Physical Reality: Processes/Threads share the same hardware – Need to multiplex CPU (CPU Scheduling) – Need to multiplex use of Memory (Today) • Why worry about memory multiplexing? – The complete working state of a process and/or kernel is defined by its data in memory (and registers) – Consequently, cannot just let different processes use the same memory – Probably don’t want different processes to even have access to each other’s memory (protection) 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 3

Important Aspects of Memory Multiplexing • Controlled overlap: – Processes should not collide in

Important Aspects of Memory Multiplexing • Controlled overlap: – Processes should not collide in physical memory – Conversely, would like the ability to share memory when desired (for communication) • Protection: – Prevent access to private memory of other processes » Different pages of memory can be given special behavior (Read Only, Invisible to user programs, etc. ) » Kernel data protected from User programs • Translation: – Ability to translate accesses from one address space (virtual) to a different one (physical) – When translation exists, process uses virtual addresses, physical memory uses physical addresses 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 4

Binding of Instructions and Data to Memory Process view of memory data 1: 32

Binding of Instructions and Data to Memory Process view of memory data 1: 32 … start: lw r 1, 0(data 1) jal checkit loop: addi r 1, -1 bnz r 1, loop … checkit: … 2/24/2014 dw Anthony D. Joseph Assume 4 byte words 0 x 300 = 4 * 0 x 0 C 0 = 0000 1100 0000 Physical addresses 0 x 300 = 0011 0000 0 x 0300 00000020 … … 0 x 0900 8 C 2000 C 0 0 x 0904 0 C 000280 0 x 0908 2021 FFFF 0 x 090 C 14200242 … 0 x 0 A 00 CS 162 ©UCB Spring 2014 9. 5

Binding of Instructions and Data to Physical Memory 0 x 0000 0 x 0300

Binding of Instructions and Data to Physical Memory 0 x 0000 0 x 0300 00000020 Process view of memory data 1: dw 32 … start: lw r 1, 0(data 1) jal checkit loop: addi r 1, -1 bnz r 1, loop … checkit: … Physical addresses 0 x 0300 … 0 x 0900 0 x 0904 0 x 0908 0 x 090 C … 0 x 0 A 00 00000020 … 8 C 2000 C 000280 2021 FFFF 14200242 0 x 0900 8 C 2000 C 000340 2021 FFFF 14200242 0 x. FFFF 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 6

Binding of Instructions and Data to Physical Memory 0 x 0000 0 x 0300

Binding of Instructions and Data to Physical Memory 0 x 0000 0 x 0300 Process view of memory data 1: dw 32 … start: lw r 1, 0(data 1) jal checkit loop: addi r 1, -1 bnz r 1, r 0, loop … checkit: … Physical addresses 0 x 300 … 0 x 900 0 x 904 0 x 908 0 x 90 C … 0 x 0 A 00 00000020 … 8 C 2000 C 000280 2021 FFFF 14200242 0 x 0900 ? App X 0 x. FFFF Need address translation! 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 7

Binding of Instructions and Data to Memory 0 x 0000 0 x 0300 Process

Binding of Instructions and Data to Memory 0 x 0000 0 x 0300 Process view of memory data 1: dw 32 … start: lw r 1, 0(data 1) jal checkit loop: addi r 1, -1 bnz r 1, r 0, loop … checkit: … Processor view of memory 0 x 1300 … 0 x 1900 0 x 1904 0 x 1908 0 x 190 C … 0 x 1 A 00 00000020 … 8 C 2004 C 0 0 C 000680 2021 FFFF 14200642 • One of many possible translations! • Where does translation take place? 0 x 0900 App X 0 x 1300 00000020 0 x 1900 8 C 2004 C 0 0 C 000680 2021 FFFF 14200642 0 x. FFFF Compile time, Link/Load time, or Execution time? 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 8

Multi-step Processing of a Program for Execution • Preparation of a program for execution

Multi-step Processing of a Program for Execution • Preparation of a program for execution involves components at: – Compile time (i. e. , “gcc”) – Link/Load time (UNIX “ld” does link) – Execution time (e. g. , dynamic libs) • Addresses can be bound to final values anywhere in this path – Depends on hardware support – Also depends on operating system • Dynamic Libraries – Linking postponed until execution – Small piece of code, stub, used to locate appropriate memory-resident library routine – Stub replaces itself with the address of the routine, and executes routine 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 9

Example of General Address Translation Data 2 Code Data Heap Stack 1 Heap 1

Example of General Address Translation Data 2 Code Data Heap Stack 1 Heap 1 Code 1 Stack 2 Prog 1 Virtual Address Space 1 Prog 2 Virtual Address Space 2 Data 1 Heap 2 Code 2 OS code Translation Map 1 OS data Translation Map 2 OS heap & Stacks 2/24/2014 Physical Address Space Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 10

Two Views of Memory CPU Virtual Addresses MMU Physical Addresses Untranslated read or write

Two Views of Memory CPU Virtual Addresses MMU Physical Addresses Untranslated read or write • Address Space: – All the addresses and state a process can touch – Each process and kernel has different address space • Consequently, two views of memory: – View from the CPU (what program sees, virtual memory) – View from memory (physical memory) – Translation box (MMU) converts between the two views • Translation helps to implement protection – If task A cannot even gain access to task B’s data, no way for A to adversely affect B • With translation, every program can be linked/loaded into same region of user address space 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 11

Uniprogramming (MS-DOS) • Uniprogramming (no Translation or Protection) – Application always runs at same

Uniprogramming (MS-DOS) • Uniprogramming (no Translation or Protection) – Application always runs at same place in physical memory since only one application at a time – Application can access any physical address Application Valid 32 -bit Addresses Operating System 0 x. FFFF 0 x 0000 – Application given illusion of dedicated machine by giving it reality of a dedicated machine 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 12

Multiprogramming (First Version) • Multiprogramming without Translation or Protection – Must somehow prevent address

Multiprogramming (First Version) • Multiprogramming without Translation or Protection – Must somehow prevent address overlap between threads Operating System Application 2 Application 1 0 x. FFFF 0 x 00020000 0 x 0000 – Trick: Use Loader/Linker: Adjust addresses while program loaded into memory (loads, stores, jumps) » Everything adjusted to memory location of program » Translation done by a linker-loader » Was pretty common in early days • With this solution, no protection: bugs in any program can cause other programs to crash or even the OS 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 13

Multiprogramming (Version with Protection) • Can we protect programs from each other without translation?

Multiprogramming (Version with Protection) • Can we protect programs from each other without translation? Operating System Application 2 Application 1 0 x. FFFF Limit. Addr=0 x 10000 0 x 00020000 Base. Addr=0 x 20000 0 x 0000 – Yes: use two special registers Base. Addr and Limit. Addr to prevent user from straying outside designated area » If user tries to access an illegal address, cause an error – During switch, kernel loads new base/limit from PCB (Process Control Block) » User not allowed to change base/limit registers 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 14

Simple Base and Bounds (CRAY-1) CPU Base Virtual Address Limit + <? DRAM Physical

Simple Base and Bounds (CRAY-1) CPU Base Virtual Address Limit + <? DRAM Physical Address No: Error! • Could use base/limit for dynamic address translation (often called “segmentation”) – translation happens at execution: – Alter address of every load/store by adding “base” – Generate error if address bigger than limit • This gives program the illusion that it is running on its own dedicated machine, with memory starting at 0 – Program gets continuous region of memory – Addresses within program do not have to be relocated when program placed in different region of DRAM 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 15

Issues with Simple Segmentation Method process 6 process 5 process 9 process 2 OS

Issues with Simple Segmentation Method process 6 process 5 process 9 process 2 OS process 6 process 9 process 11 process 10 OS OS OS • Fragmentation problem – Not every process is the same size – Over time, memory space becomes fragmented • Hard to do inter-process sharing – Want to share code segments when possible – Want to share memory between processes – Helped by providing multiple segments per process 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 16

More Flexible Segmentation 1 1 4 1 2 3 2 2 4 3 user

More Flexible Segmentation 1 1 4 1 2 3 2 2 4 3 user view of memory space physical memory space • Logical View: multiple separate segments – Typical: Code, Data, Stack – Others: memory sharing, etc • Each segment is given region of contiguous memory – Has a base and limit – Can reside anywhere in physical memory 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 17

Implementation of Multi-Segment Model Virtual Seg # Offset Address offset Base 0 Base 1

Implementation of Multi-Segment Model Virtual Seg # Offset Address offset Base 0 Base 1 Base 2 Base 3 Base 4 Base 5 Base 6 Base 7 Limit 0 Limit 1 Limit 2 Limit 3 Limit 4 Limit 5 Limit 6 Limit 7 V V V N N V > Error + Physical Address Check Valid • Segment map resides in processor Access – Segment number mapped into base/limit pair – Base added to offset to generate physical address Error – Error check catches offset out of range • As many chunks of physical memory as entries – Segment addressed by portion of virtual address – However, could be included in instruction instead: » x 86 Example: mov [es: bx], ax. • What is “V/N” (valid / not valid)? – Can mark segments as invalid; requires check as well 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 18

Example: Four Segments (16 bit addresses) Seg Offset 15 14 13 0 Virtual Address

Example: Four Segments (16 bit addresses) Seg Offset 15 14 13 0 Virtual Address Format 0 x 0000 0 x 4000 Seg. ID = 1 Seg ID # 0 (code) 1 (data) 2 (shared) 3 (stack) Base 0 x 4000 0 x 4800 0 x. F 000 0 x 0000 Limit 0 x 0800 0 x 1400 0 x 1000 0 x 3000 0 x 0000 0 x 4800 0 x 5 C 00 Might be shared 0 x 8000 Space for Other Apps 0 x. C 000 0 x. F 000 Virtual Address Space 2/24/2014 Anthony D. Joseph Physical Address Space CS 162 ©UCB Spring 2014 Shared with Other Apps 9. 19

Schematic View of Swapping • Q: What if not all processes fit in memory?

Schematic View of Swapping • Q: What if not all processes fit in memory? • A: Swapping: Extreme form of Context Switch – In order to make room for next process, some or all of the previous process is moved to disk – This greatly increases the cost of context-switching • Desirable alternative? – Some way to keep only active portions of a process in memory at any one time – Need finer granularity control over physical memory 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 20

Problems with Segmentation • Must fit variable-sized chunks into physical memory • May move

Problems with Segmentation • Must fit variable-sized chunks into physical memory • May move processes multiple times to fit everything • Limited options for swapping to disk • Fragmentation: wasted space – External: free gaps between allocated chunks – Internal: don’t need all memory within allocated chunks 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 21

Administrivia • Project #1 code due Tuesday Feb 25 by 11: 59 pm •

Administrivia • Project #1 code due Tuesday Feb 25 by 11: 59 pm • Design doc (submit proj 1 -final-design) and group evals (Google Docs form) due Wed 2/26 at 11: 59 PM 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 22

5 min Break 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 23

5 min Break 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 23

Paging: Physical Memory in Fixed Size Chunks • Solution to fragmentation from segments? –

Paging: Physical Memory in Fixed Size Chunks • Solution to fragmentation from segments? – Allocate physical memory in fixed size chunks (“pages”) – Every chunk of physical memory is equivalent » Can use simple vector of bits to handle allocation: 00110001101 … 110010 » Each bit represents page of physical memory 1 allocated, 0 free • Should pages be as big as our previous segments? – No: Can lead to lots of internal fragmentation » Typically have small pages (1 K-16 K) – Consequently: need multiple pages/segment 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 24

How to Implement Paging? Virtual Address: Page # Offset Page. Table. Ptr Page. Table.

How to Implement Paging? Virtual Address: Page # Offset Page. Table. Ptr Page. Table. Size > Access Error page #0 page #1 page #2 page #3 page #4 page #5 V, R, W N V, R, W Physical Page # Offset Physical Address Check Perm • Page Table (One per process) Access Error – Resides in physical memory – Contains physical page and permission for each virtual page » Permissions include: Valid bits, Read, Write, etc • Virtual address mapping – Offset from Virtual address copied to Physical Address » Example: 10 bit offset 1024 -byte pages – Virtual page # is all remaining bits » Example for 32 -bits: 32 -10 = 22 bits, i. e. 4 million entries » Physical page # copied from table into physical address – Check Page Table bounds and permissions 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 25

What about Sharing? Virtual Address (Process A): Virtual Page # Page. Table. Ptr. A

What about Sharing? Virtual Address (Process A): Virtual Page # Page. Table. Ptr. A Page. Table. Ptr. B Virtual Address (Process B): 2/24/2014 Virtual Page # Anthony D. Joseph Offset page #0 page #1 page #2 page #3 page #4 page #5 V, R, W N V, R, W page #0 page #1 page #2 page #3 page #4 page #5 V, R N V, R, W Shared Page This physical page appears in address space of both processes Offset CS 162 ©UCB Spring 2014 9. 26

Simple Page Table Example (4 byte pages) a b c 0 x 04 d

Simple Page Table Example (4 byte pages) a b c 0 x 04 d e f 0 x 06? g 0 x 08 h i 0 x 09? j k l 0 x 00 0000 0 x 00 0 0000 0100 0000 1000 Virtual Memory 0001 0000 4 1 3 2 1 0 x 04 0000 1100 0000 0100 Page Table 0 x 08 0 x 0 C 0000 0110 0000 1001 0000 0101 0 x 10 i j k l e f g h a b c d 0 x 05! 0 x 0 E! Physical Memory 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 27

Page Table Discussion • What needs to be switched on a context switch? –

Page Table Discussion • What needs to be switched on a context switch? – Page table pointer and limit • Analysis – Pros » Simple memory allocation » Easy to Share – Con: What if address space is sparse? » E. g. on UNIX, code starts at 0, stack starts at (231 -1). » With 1 K pages, need 2 million page table entries! – Con: What if table really big? » Not all pages used all the time would be nice to have working set of page table in memory • How about combining paging and segmentation? 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 28

Multi-level Translation • What about a tree of tables? – Lowest level page table

Multi-level Translation • What about a tree of tables? – Lowest level page table memory still allocated with bitmap – Higher levels often segmented • Could have any number of levels. Example (top segment): Virtual Address: Virtual Seg # Base 0 Base 1 Base 2 Base 3 Base 4 Base 5 Base 6 Base 7 Virtual Page # Limit 0 Limit 1 Limit 2 Limit 3 Limit 4 Limit 5 Limit 6 Limit 7 V V V N N V Offset page #0 page #1 page #2 page #3 page #4 page #5 > Access Error V, R, W N V, R, W Physical Page # Offset Physical Address Check Perm Access Error • What must be saved/restored on context switch? – Contents of top-level segment registers (for this example) – Pointer to top-level table (page table) 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 29

What about Sharing (Complete Segment)? Process A Virtual Seg # Base 0 Base 1

What about Sharing (Complete Segment)? Process A Virtual Seg # Base 0 Base 1 Base 2 Base 3 Base 4 Base 5 Base 6 Base 7 Process B 2/24/2014 Virtual Page # Limit 0 Limit 1 Limit 2 Limit 3 Limit 4 Limit 5 Limit 6 Limit 7 Virtual Seg # V V V N N V Virtual Page # Anthony D. Joseph Offset page #0 page #1 page #2 page #3 page #4 page #5 V, R, W N V, R, W Shared Segment Base 0 Base 1 Base 2 Base 3 Base 4 Base 5 Base 6 Base 7 Limit 0 Limit 1 Limit 2 Limit 3 Limit 4 Limit 5 Limit 6 Limit 7 V V V N N V Offset CS 162 ©UCB Spring 2014 9. 30

Another common example: two-level page table 10 bits Virtual Address: 10 bits 12 bits

Another common example: two-level page table 10 bits Virtual Address: 10 bits 12 bits Virtual P 1 index P 2 index Offset Physical Address: Physical Offset Page # 4 KB Page. Table. Ptr 4 bytes • Tree of Page Tables • Tables fixed size (1024 entries) – On context-switch: save single Page. Table. Ptr register • Valid bits on Page Table Entries – Don’t need every 2 nd-level table – Even when exist, 2 nd-level tables can reside on disk if not in use 2/24/2014 Anthony D. Joseph CS 162 4 bytes ©UCB Spring 2014 9. 31

Multi-level Translation Analysis • Pros: – Only need to allocate as many page table

Multi-level Translation Analysis • Pros: – Only need to allocate as many page table entries as we need for application – size is proportional to usage » In other words, sparse address spaces are easy – Easy memory allocation – Easy Sharing » Share at segment or page level (need additional reference counting) • Cons: – One pointer page (typically 4 K – 16 K pages today) – Page tables need to be contiguous » However, previous example keeps tables to exactly one page in size – Two (or more, if >2 levels) lookups per reference » Seems very expensive! 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 32

Inverted Page Table • With all previous examples (“Forward Page Tables”) – Size of

Inverted Page Table • With all previous examples (“Forward Page Tables”) – Size of page tables is at least as large as amount of virtual memory allocated to ALL processes – Physical memory may be much, much less » Much of process’ space may be out on disk or not in use Virtual Page # Process ID Offset Physical Page # Offset Hash Table • Answer: use a hash table – Called an “Inverted Page Table” – Size is independent of virtual address space – Directly related to amount of phy mem (1 entry per phy page) – Very attractive option for 64 -bit address spaces (IA 64, Power. PC, Ultra. SPARC) • Cons: Complexity of managing hash chains in hardware 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 33

Summary: Address Segmentation Virtual memory view 1111 stack 1111 0000 (0 x. F 0)

Summary: Address Segmentation Virtual memory view 1111 stack 1111 0000 (0 x. F 0) 1100 0000 (0 x. C 0) 1000 0000 (0 x 80) heap 1011 0000 + 11 0000 -------1110 0000 Seg # base 11 1011 0000 10 0111 0000 1 1000 01 0101 0000 10 0000 00 0001 0000 10 0000 Physical memory view stack limit heap data 0100 0000 (0 x 40) data code 0000 1110 0000 (0 x. E 0) code 0111 0000 (0 x 70) 0101 0000 (0 x 50) 0001 0000 (0 x 10) 0000 seg # offset 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 34

Summary: Address Segmentation Virtual memory view 1111 1110 0000 Physical memory view stack 1100

Summary: Address Segmentation Virtual memory view 1111 1110 0000 Physical memory view stack 1100 0000 What happens if stack grows to 1110 0000? heap 1000 0000 stack Seg # base 11 1011 0000 10 0111 0000 1 1000 01 0101 0000 10 0000 00 0001 0000 10 0000 limit heap data 0100 0000 data code 0000 1110 0000 code 0111 0000 0101 0000 0000 seg # offset 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 35

Recap: Address Segmentation Virtual memory view 1111 1110 0000 stack 1100 0000 1000 0100

Recap: Address Segmentation Virtual memory view 1111 1110 0000 stack 1100 0000 1000 0100 0000 Physical memory view heap stack Seg # base 11 1011 0000 10 0111 0000 1 1000 01 0101 0000 00 0001 0000 data limit No 10 0000 room to grow!! Buffer overflow error or 10 0000 heap and 0111 0000 resize segment move segments around data to make room 0101 0000 code 0000 1110 0000 code 0001 0000 seg # offset 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 36

Summary: Paging Virtual memory view 1111 stack 1111 0000 1100 0000 heap 1000 0000

Summary: Paging Virtual memory view 1111 stack 1111 0000 1100 0000 heap 1000 0000 data 0100 0000 code 0000 page # offset 2/24/2014 Anthony D. Joseph Page Table 11111 11101 111101 null 11100 null 11011 null 11010 null 11001 null 11000 null 10111 null 10110 null 10101 null 10100 null 10011 null 10010 10001 01111 10000 01111 null 01110 null 01101 null 01100 null 01011 01101 01010 01100 01001 01011 01000 01010 00111 null 00110 null 00101 null 00100 null 00011 00101 000100 000011 CS 162 00000 00010 111 01 Physical memory view 111 stack heap data code ©UCB Spring 2014 1110 0000 0111 000 0101 0001 0000 9. 37

Summary: Paging Virtual memory view 1111 stack 1110 0000 1100 0000 What happens if

Summary: Paging Virtual memory view 1111 stack 1110 0000 1100 0000 What happens if stack grows to 1110 0000? heap 1000 0000 data 0100 0000 code 0000 page # offset 2/24/2014 Anthony D. Joseph Page Table 11111 11101 111101 null 11100 null 11011 null 11010 null 11001 null 11000 null 10111 null 10110 null 10101 null 10100 null 10011 null 10010 10001 01111 10000 01111 null 01110 null 01101 null 01100 null 01011 01101 01010 01100 01001 01011 01000 01010 00111 null 00110 null 00101 null 00100 null 00011 00101 000100 000011 CS 162 00000 00010 Physical memory view stack heap data code ©UCB Spring 2014 1110 0000 0111 000 0101 0001 0000 9. 38

Summary: Paging Virtual memory view 1111 stack 1110 0000 1100 0000 heap 1000 0000

Summary: Paging Virtual memory view 1111 stack 1110 0000 1100 0000 heap 1000 0000 data 0100 0000 code 0000 page # offset 2/24/2014 Anthony D. Joseph Page Table 11111 11101 111101 10111 11100 10110 11011 null 11010 null 11001 null 11000 null 10111 null 10110 null 10101 null 10100 null 10011 null 10010 10001 01111 10000 01111 null 01110 null 01101 null 01100 null 01011 01101 01010 01100 01001 01011 01000 01010 00111 null 00110 null 00101 null 00100 null 00011 00101 000100 000011 CS 162 00000 00010 Physical memory view stack 1110 0000 stack Allocate new pages where heap room! 0111 000 data code ©UCB Spring 2014 0101 0001 0000 9. 39

Summary: Two-Level Paging Virtual memory view 1111 Page Tables (level 2) stack 1111 0000

Summary: Two-Level Paging Virtual memory view 1111 Page Tables (level 2) stack 1111 0000 Page Table (level 1) 1100 0000 1000 0100 0000 page 2 # 0000 heap 111 110 101 100 011 010 001 000 null 11 10 01 00 11101 11100 10111 10110 11 null 10 10000 01 01111 00 01110 null Physical memory view stack heap null data 11 10 01 00 01101 01100 01011 01010 code 11 10 01 00 00101 00100 00011 00010 1110 0000 data code 0111 000 0101 0001 0000 page 1 # offset 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 40

Summary: Two-Level Paging Virtual memory view Page Tables (level 2) stack Page Table (level

Summary: Two-Level Paging Virtual memory view Page Tables (level 2) stack Page Table (level 1) 1001 0000 (0 x 90) 2/24/2014 heap 111 110 101 100 011 010 001 000 null 11 10 01 00 11101 11100 10111 10110 11 null 10 10000 01 01111 00 01110 null stack data 01101 01100 01011 01010 code 11 10 01 00 00101 00100 00011 00010 CS 162 1110 0000 stack heap null 11 10 01 00 Anthony D. Joseph Physical memory view 1000 0000 (0 x 80) data code ©UCB Spring 2014 0001 0000 9. 41

Summary: Inverted Table Virtual memory view 1111 stack 1110 0000 Physical memory view Inverted

Summary: Inverted Table Virtual memory view 1111 stack 1110 0000 Physical memory view Inverted Table Hash(proc. ID & virt. page #) = phys. page # 1100 0000 heap 1000 0000 data 0100 0000 h(11111) = 11101 h(11110) = 11100 h(11101) = 10111 h(11100) = 10110 h(10010)= 10000 h(10001)= 01111 h(10000)= 01110 h(01011)= 01101 h(01010)= 01100 h(01001)= 01011 h(01000)= 01010 h(00011)= 00101 h(00010)= 00100 h(00001)= 00011 h(00000)= 00010 stack 1110 0000 stack 1011 0000 heap data code 0000 0111 0000 0101 0000 0000 page # offset 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 42

Address Translation Comparison Advantages Disadvantages Segmentation Fast context External fragmentation switching: Segment mapping maintained

Address Translation Comparison Advantages Disadvantages Segmentation Fast context External fragmentation switching: Segment mapping maintained by CPU Paging (single No external -level page) fragmentation, fast easy allocation Large table size ~ virtual memory Paged Table size ~ # of segmentation pages in virtual memory, fast easy Two-level allocation pages Multiple memory references per page access Inverted Table size ~ # of pages in physical 2/24/2014 Anthony D. memory Joseph CS 162 Hash function more complex ©UCB Spring 2014 9. 43

Summary • Memory is a resource that must be multiplexed – Controlled Overlap: only

Summary • Memory is a resource that must be multiplexed – Controlled Overlap: only shared when appropriate – Translation: Change virtual addresses into physical addresses – Protection: Prevent unauthorized sharing of resources • Simple Protection through segmentation – Base + Limit registers restrict memory accessible to user – Can be used to translate as well • Page Tables – Memory divided into fixed-sized chunks of memory – Offset of virtual address same as physical address • Multi-Level Tables – Virtual address mapped to series of tables – Permit sparse population of address space • Inverted page table: size of page table related to physical memory size 2/24/2014 Anthony D. Joseph CS 162 ©UCB Spring 2014 9. 44