Crosstalk Noise Optimization by PostLayout Transistor Sizing Masanori

Crosstalk Noise Optimization by Post-Layout Transistor Sizing Masanori Hashimoto Masao Takahashi Hidetoshi Onodera Dept. CCE, Kyoto University 1

Post-Layout Tr. Sizing for Crosstalk Noise Reduction Overview Crosstalk noise depends on • coupling length • coupling position Routing & interconnect optimization • driver strength of aggressor • hold strength of victim n Use analytic noise model n n Our target suitable for a lot of repetitive noise estimation Optimize Tr. sizes preserving interconnects n no iterations between Tr. sizing and layout 2

Post-Layout Tr. Sizing for Crosstalk Noise Reduction Features Optimization with interconnect preservation n no iterations between layout and Tr. sizing n accurately-extracted coupling information Downsize too strong drivers n n n continuous sizing vary PN ratio consider noise margin and transition time constraints 3

On-Demand Cell Layout Generation(VARDS) Half size Normal size Same height Shrink Tr. width Terminals are fixed. 4

Contents n n Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion 5

Generic RC Trees on LSI Multiple aggressors, multiple branches aggressor 1 branch 2 branch 1 aggressor 2 victim aggressor 3 6

Crosstalk Noise Estimation　Overview n Noise estimation for two partially-coupled interconnects n n Multiple aggressors n n closed-form noise waveform Aggressor Victim superpose noises from each aggressor Multiple sinks n transform into two partially-coupled interconnects 7

Modeling of Two Partially. Coupled Interconnects aggressor model Vagg(t) Vnoise(t) victim model 8

Noise Waveform and Peak Noise Voltage noise waveform peak noise Vagg Rv 1 Cv 1 Rv 2 Cc Rv 3 Vnoise Cv 3 9

Multiple Aggressors aggressor 1 victim Vnoise(t) aggressor n aggressor 1 Vnoisen(t) Vnoise 1(t) aggressor n Superposition Vnoise(t)=Vnoise 1(t)+・・・+Vnoisen(t) 10

Superposition Considering Timing Window Superposition of peak noise Eliminate pessimistic estimation using timing window fastest arrival time t latest arrival time (timing window) other Timing window calculation Fastest arrival time: STA with coupling cap. multiplied by -1 Latest arrival time: STA with coupling cap. multiplied by 3 [P. Chen, et. al. , ICCAD 2000] 11

Contents n n Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion 12

Optimization Algorithm in Each Victim Net aggressor downsize timing margin noise voltage High priority victim start strong impact and loose timing constraint n Downsize Tr. n Select agg. net with max-priority from non-optimized net. 2 2 n Downsize Tr. such that Va +Vv is minimum. Consider both noises at aggressor and victim Finish? n Calculate priorityi Downsize Tr. Finish？ Y end N n n All aggressors are optimized? Noise is smaller than Vtarget? 13

Overall Optimization Algorithm start n Calculate noise n Put nets into L n Y end N n n Put nets(> threshold・Vmax) into list L. Execute local opt. n Execute local opt. Finish？ Put nets into L Optimize net with max-noise in L. threshold・Vmax is target value Vtarget. Finish? n Global optimality L is empty? Execute several times, decreasing threshold. 1 threshold 0 Peak noise reduction Most of nets are optimized. 14

Contents n n Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion 15

Experimental Conditions n n 0. 35 mm technology Two combinational circuits designed for minimizing delay n n n RC extraction n dsp_alu: 2. 3 x 2. 3 mm 2, 13 k cells des: 0. 8 x 0. 8 mm 2, 3 k cells Small coupling caps. (<10 f. F) are treated as caps. to ground. Supply voltage: 3. 3 V Cell height: 13 routing pitches n Tr. Width: 6. 2 mm(standard), 0. 9 mm(minimum) 16

Optimization Results of Crosstalk Noise Reduction Optimize noise without delay increase des circuit dsp_alu 0. 40 -> 0. 19 peak noise[V] 1. 00 -> 0. 50 12 CPU time[s] 604 3. 4 k #cells 13 k 17

Initial and Optimized Layouts Initial Optimized 18

Accuracy of Peak Noise Estimation n n All coupled interconnects in des circuit Actual interconnects with branches driven by CMOS gates Average error: 10 m. V 19

Conclusion n Propose crosstalk noise reduction method by post-layout Tr. sizing n n use analytic noise model downsize too strong aggressors preserve interconnects completely reduce peak noise by 50% 20